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18 条记录 (耗时 0.013 秒)

    Flex circuit for accessing pins of a chip carrier
    1.
    发明授权
    Flex circuit for accessing pins of a chip carrier 有权

    公开(公告)号：US10269696B2

    公开(公告)日：2019-04-23

    申请号：US14965831

    申请日：2015-12-10

    申请人： Intel Corporation

    发明人： Gerrit John Vreman ,  Animesh Mishra

    IPC分类号： H01R9/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H05K1/02 ,  H05K1/11

    摘要： Flexible circuits mountable in a standoff region between a chip carrier, e.g., a ball grid array (BGA) component, and a printed circuit board (PCB) of a surface-mount package are described. In an example, a flexible circuit includes holes to receive pins, e.g., solder balls, of the BGA component, and one or more conductive leads electrically connected to respective solder balls within the holes. The conductive leads may interconnect several solder balls within the standoff region, and may be electrically accessible through a test pad located laterally outward from the standoff region. Electrical signals may be monitored or driven through the test pad, and thus, the flexible circuit may be used as a debug tool for detecting and or correcting a design fault of the surface-mount package.

    Dynamic core swapping
    10.
    发明授权
    Dynamic core swapping 有权
    动态核心交换

    公开(公告)号：US08949633B2

    公开(公告)日：2015-02-03

    申请号：US13938150

    申请日：2013-07-09

    申请人： Intel Corporation

    发明人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

    IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F15/80

    CPC分类号： G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

    摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

    摘要翻译： 本发明的实施例是用于动态地交换处理器核心的技术。 第一个核心有一个第一个指令集。 第一个核心以第一个性能级别执行程序。 当触发事件发生时，第一个内核停止执行程序。 第二核心具有与第一指令集兼容的第二指令集，并且具有与第一性能级别不同的第二性能级别。 当第一个核心执行程序时，第二个内核处于掉电状态。 在第一核心停止执行程序之后，电路对第二核心供电，使得第二核心继续在第二性能级别执行程序。