公开(公告)号：US10192612B2

公开(公告)日：2019-01-29

申请号：US15550898

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Jingqiu Wang ,  Li Liu ,  Liang Chen

IPC: G11C11/417 ,  G11C11/413 ,  G11C11/412

Abstract: The present invention provides a memory cell of a static random access memory based on resistance reinforcement, which includes a latch circuit and a bit selection circuit. The latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network. The bit selection circuit consists of NMOS transistors N5 and N6. The latch circuit form four storage nodes X1, X1B, X2, X2B. Compared to the conventional memory cell of a 6T structure, a resistance-capacitance network is added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset at a cost of increasing a small amount of area, thus ensuring correctness of data.

公开(公告)号：US10121535B2

公开(公告)日：2018-11-06

申请号：US15551008

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Jingqiu Wang ,  Liang Chen ,  Li Liu

IPC: G11C11/34 ,  G11C11/417 ,  H01L27/11 ,  G11C11/412

Abstract: The memory cell of static random access memory based on resistance-capacitance reinforcement, which comprises a latch circuit and a bit selection circuit, the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network; the bit selection circuit consists of NMOS transistors N5 and N6; the latch circuit forms four storage nodes X1, X1B, X2, X2B, among which a coupling capacitor C is provided between a pair of complementary data storage nodes. Compared to the conventional memory cell of 6T structure, a resistance-capacitance network and a coupling capacitor are added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset merely at a cost of increasing a small amount of area, thus ensuring correctness of data.

公开(公告)号：US20180174648A1

公开(公告)日：2018-06-21

申请号：US15551024

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Li Liu ,  Jingqiu Wang ,  Liang Chen

IPC: G11C11/419 ,  H01L27/11 ,  G06F3/06

CPC classification number: G11C11/419 ,  G06F3/0619 ,  G11C11/4125 ,  G11C29/74 ,  H01L27/11

Abstract: The present invention provides a memory cell of a static random access memory based on DICE structure, which comprises a redundant information latch circuit and a redundant bit selection circuit; the redundant information latch circuit is formed by four MOS transistors and includes four data storage nodes; the redundant bit selection circuit is also formed by four MOS transistors M0, M1, M2 and M3, with their drains connected to the four data storage nodes X0, X1, X2 and X3; wherein sources of M0 and M2 are connected to each other and are connected to a bit line BL, sources of M1 and M3 are connected to each other and are connected to a bit line BLB; and gates of the four MOS transistors are connected to each other and are connected to a word line WL. By means of the present invention, without obviously increasing complexity and merely increasing a small amount of area, the memory cell can be prevented from having a state reversal when hit by particles, thus ensuring correctness of data.

公开(公告)号：US20180025774A1

公开(公告)日：2018-01-25

申请号：US15550898

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Jingqiu Wang ,  Li Liu ,  Liang Chen

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/413

Abstract: The present invention provides a memory cell of a static random access memory based on resistance reinforcement, which includes a latch circuit and a bit selection circuit. The latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network. The bit selection circuit consists of NMOS transistors N5 and N6. The latch circuit form four storage nodes X1, X1B, X2, X2B. Compared to the conventional memory cell of a 6T structure, a resistance-capacitance network is added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset at a cost of increasing a small amount of area, thus ensuring correctness of data.

公开(公告)号：US10262724B2

公开(公告)日：2019-04-16

申请号：US15551024

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Li Liu ,  Jingqiu Wang ,  Liang Chen

IPC: G11C11/419 ,  G06F3/06 ,  H01L27/11 ,  G11C11/412 ,  G11C29/00

Abstract: A memory cell of a static random access memory based on DICE structure, which includes a redundant information latch circuit and a redundant bit selection circuit. The redundant information latch circuit is formed by four MOS transistors and includes four data storage nodes, the redundant bit selection circuit is formed by four MOS transistors M0, M1, M2 and M3, with their drains connected to the four data storage nodes X0, X1, X2 and X3. Sources of M0 and M2 are connected to each other and are connected to a bit line BL, sources of M1 and M3 are connected to each other and are connected to a bit line BLB; and gates of the four MOS transistors are connected to each other and are connected to a word line WL.

公开(公告)号：US20180166125A1

公开(公告)日：2018-06-14

申请号：US15551008

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Jingqiu Wang ,  Liang Chen ,  Li LIU

IPC: G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/4125 ,  H01L27/1104

Abstract: The present invention provides a memory cell of static random access memory based on resistance-capacitance reinforcement, which comprises a latch circuit and a bit selection circuit, the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network; the bit selection circuit consists of NMOS transistors N5 and N6; the latch circuit forms four storage nodes X1, X1B, X2, X2B, among which a coupling capacitor C is provided between a pair of complementary data storage nodes. Compared to the conventional memory cell of 6T structure, a resistance-capacitance network and a coupling capacitor are added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset merely at a cost of increasing a small amount of area, thus ensuring correctness of data.