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公开(公告)号:US20240312936A1
公开(公告)日:2024-09-19
申请号:US18604787
申请日:2024-03-14
Applicant: Infineon Technologies Austria AG
Inventor: Joon Shyan Tan , Lee Shuang Wang , Azlina Kassim , Teck Sim Lee , Kok Yau Chua , Chee Hong Lee , Zhihui Yuan
IPC: H01L23/00 , H01L23/31 , H01L23/498 , H01L25/00 , H01L25/065
CPC classification number: H01L24/08 , H01L23/3107 , H01L23/49838 , H01L25/0655 , H01L25/50 , H01L24/45 , H01L24/48 , H01L2224/08225 , H01L2224/45014 , H01L2224/48175 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19101
Abstract: A power semiconductor package includes: a first power semiconductor die arranged on and electrically coupled to a first side of a first die pad; a first passive electronic component having a first end and an opposite second end, the first end being arranged on and coupled to the first side of the first die pad and the second end being coupled to an internal ledge of a first external contact; a second passive electronic component connected in series with the first passive electronic component; and an encapsulation encapsulating the first power semiconductor die and the first and second passive electronic components. The first external contact is exposed from a first lateral side of the encapsulation.
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公开(公告)号:US12080625B2
公开(公告)日:2024-09-03
申请号:US18235668
申请日:2023-08-18
Applicant: Infineon Technologies Austria AG
Inventor: Li Fong Chong , Yee Beng Daryl Yeow , Chii Shang Hong , Azlina Kassim , Hui Kin Lit
IPC: H01L23/495 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/433
CPC classification number: H01L23/4334 , H01L21/561 , H01L21/565 , H01L23/315 , H01L23/49503 , H01L23/562 , H01L24/32 , H01L24/48 , H01L2224/32245 , H01L2224/48245
Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
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公开(公告)号:US20230395462A1
公开(公告)日:2023-12-07
申请号:US18235668
申请日:2023-08-18
Applicant: Infineon Technologies Austria AG
Inventor: Li Fong Chong , Yee Beng Daryl Yeow , Chil Shang Hong , Azlina Kassim , Hui Kin Lit
IPC: H01L23/433 , H01L21/56 , H01L23/31 , H01L23/495 , H01L23/00
CPC classification number: H01L23/4334 , H01L21/561 , H01L21/565 , H01L23/315 , H01L23/49503 , H01L23/562 , H01L24/32 , H01L24/48 , H01L2224/32245 , H01L2224/48245
Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
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公开(公告)号:US11791238B2
公开(公告)日:2023-10-17
申请号:US17355342
申请日:2021-06-23
Applicant: Infineon Technologies Austria AG
Inventor: Li Fong Chong , Yee Beng Daryl Yeow , Chii Shang Hong , Azlina Kassim , Hui Kin Lit
IPC: H01L23/495 , H01L23/433 , H01L21/56 , H01L23/31 , H01L23/00
CPC classification number: H01L23/4334 , H01L21/561 , H01L21/565 , H01L23/315 , H01L23/49503 , H01L23/562 , H01L24/32 , H01L24/48 , H01L2224/32245 , H01L2224/48245
Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
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公开(公告)号:US20220415753A1
公开(公告)日:2022-12-29
申请号:US17355342
申请日:2021-06-23
Applicant: Infineon Technologies Austria AG
Inventor: Li Fong Chong , Yee Beng Daryl Yeow , Chii Shang Hong , Azlina Kassim , Hui Kin Lit
IPC: H01L23/433 , H01L23/31 , H01L23/495 , H01L23/00 , H01L21/56
Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
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