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    Digital frequency synthesizer with robust injection locked divider
    1.
    发明授权
    Digital frequency synthesizer with robust injection locked divider 有权

    公开(公告)号：US10135452B2

    公开(公告)日：2018-11-20

    申请号：US15438438

    申请日：2017-02-21

    Applicant: Infineon Technologies AG ,  Politecnico Di Milano

    Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

    IPC: H03L7/24 ,  H03L7/099 ,  H03B5/12

    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

    Digital frequency synthesizer with robust injection locked divider
    5.
    发明授权
    Digital frequency synthesizer with robust injection locked divider 有权

    公开(公告)号：US10826508B2

    公开(公告)日：2020-11-03

    申请号：US16189949

    申请日：2018-11-13

    Applicant: Infineon Technologies AG ,  Politecnico Di Milano

    Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

    IPC: H03L7/24 ,  H03B5/12 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

    Phase locked loop with parallel phase detection circuits
    7.
    发明授权
    Phase locked loop with parallel phase detection circuits 有权

    公开(公告)号：US11418199B1

    公开(公告)日：2022-08-16

    申请号：US17327049

    申请日：2021-05-21

    Applicant: Infineon Technologies AG ,  Politecnico Di Milano

    Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Alessio Santiccioli

    IPC: H03L7/087 ,  H03L7/099 ,  H04L7/033

    Abstract: In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

    Digital phase-locked loop with a dynamic element matching circuit and a digitally controlled oscillator
    10.
    发明授权
    Digital phase-locked loop with a dynamic element matching circuit and a digitally controlled oscillator 有权

    公开(公告)号：US11184013B1

    公开(公告)日：2021-11-23

    申请号：US17181366

    申请日：2021-02-22

    Applicant: Infineon Technologies AG

    Inventor： Luigi Grimaldi ,  Giovanni Boi ,  Dmytro Cherniak ,  Fabio Padovan

    IPC: H03L7/099 ,  H03L7/093

    Abstract: A method of operating a phase-locked loop (PLL) having a dynamic element matching (DEM)-driven digitally controlled oscillator (DCO) includes calibrating the PLL, where calibrating the PLL includes opening a loop of the PLL and performing linearity measurements of the DEM-driven DCO when the loop of the PLL is open and when dynamic matching of the DEM-driven DCO is activated, where performing the linearity measurements includes: applying test control words to the DEM-driven DCO to obtain frequencies in a first range of frequencies; and measuring output frequencies of the DEM-driven DCO corresponding to the test control words. Calibrating the PLL further includes calculating calibration information based on the test control words and the measured output frequencies.

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