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    Integrated DRAM memory cell and DRAM memory
    1.
    发明申请
    Integrated DRAM memory cell and DRAM memory 有权
    集成DRAM存储单元和DRAM存储器

    公开(公告)号：US20010036102A1

    公开(公告)日：2001-11-01

    申请号：US09801715

    申请日：2001-03-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Alexander Frey ,  Werner Weber ,  Till Schlosser

    IPC: G11C011/24

    CPC classification number: H01L27/10882 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10897

    Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another. To achieve, with increasing miniaturization of the DRAM memory patterns, during the transition from so-called nullfoldednull bit line architectures to so-called nullopennull bit line architectures that the bit line grid, and thus also the grid of corresponding read/write amplifiers, varies linearly in scale with the longitudinal extent (L) of the memory cells (51), it is provided according to the invention that the bit lines (55) are now oriented perpendicularly to the longitudinal extent (L) of the memory cells (51) in the direction of the lateral extent (B) of the memory cells (51)

    Abstract translation: 描述了具有多个DRAM存储单元（51）的DRAM存储器（50），每个情况下的存储单元（51）具有存储电容器（52）和选择晶体管（12） 至少基本上矩形的单元区域（59），所述单元区域（59）在纵向方向（L）上比在宽度方向（B）上具有更大的程度，并且它们被布线或可以经由字连接到单元周边 线（56,57）和位线（55）。 字线（56,57）和位线（55）在存储器单元（51）上传导，并且至少基本上彼此垂直定向。 为了实现随着DRAM存储器模式的小型化，在从所谓的“折叠”位线结构转变到所谓的“开放”位线架构，即位线格栅，从而也是对应读/ 写放大器随着存储器单元（51）的纵向延伸（L）而在尺度上线性变化，根据本发明，提供了位线（55）垂直于存储器的纵向延伸（L）定向 在存储单元（51）的横向范围（B）的方向上的单元（51）

    Semiconductor device and corresponding fabrication method
    3.
    发明申请
    Semiconductor device and corresponding fabrication method 失效
    半导体器件及相应的制造方法

    公开(公告)号：US20040229424A1

    公开(公告)日：2004-11-18

    申请号：US10777207

    申请日：2004-02-13

    Applicant: Infineon Technologies AG

    Inventor： Bjorn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlosser

    IPC: H01L021/8238

    CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/31612 ,  H01L21/31616 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/56 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/785

    Abstract: A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

    Abstract translation: 具有栅极结构的半导体器件，所述栅极结构具有由第一材料制成的第一栅极电介质，所述第一材料具有位于所述沟道区域正上方的第一厚度和第一介电常数，以及由第二栅极电介质构成的覆盖的第二栅极电介质 具有第二厚度和第二介电常数的材料，其显着大于第一介电常数; 并且第一栅极电介质的第一厚度和第二栅极电介质的第二厚度被选择为使得具有第一栅极电介质的栅极结构的相应厚度以获得相同的阈值电压至少与 厚度等于第一厚度和第二厚度之和的厚度。 本发明还涉及相应的制造方法。

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