公开(公告)号：US20130193591A1

公开(公告)日：2013-08-01

申请号：US13749884

申请日：2013-01-25

申请人： Infineon Technologies AG

发明人： Torsten Groening ,  Mark Essert ,  Christian Steininger ,  Roman Lennart Tschirbs

IPC分类号： H01L23/40 ,  H01L21/50

CPC分类号： H01L23/40 ,  H01L21/4878 ,  H01L21/50 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3735 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.

摘要翻译： 功率半导体模块包括具有顶面，下侧和形成在基板中的凹陷的基板。 凹陷延伸到从顶部进行的底板。 底板的厚度在凹陷区域局部减小。 功率半导体模块还包括布置在基板的顶侧上的凹陷上方的电路载体，使得凹陷插入电路载体和底板的下侧之间。

公开(公告)号：US20160001393A1

公开(公告)日：2016-01-07

申请号：US14751361

申请日：2015-06-26

申请人： Infineon Technologies AG

发明人： Mark Essert ,  Marianna Nomann ,  Thomas Nuebel ,  Guido Strotmann

IPC分类号： B23K20/10 ,  B23K20/22

CPC分类号： B23K20/10 ,  B23K20/22 ,  B23K2101/38 ,  H05K1/0263 ,  H05K1/0306 ,  H05K3/328 ,  H05K2203/0285

摘要： One aspect of the invention relates to a method for producing a circuit carrier. For this purpose, an electrically insulating carrier is provided, having an upper side and also an underside opposite from the upper side. A first metal foil and a hardening material are likewise provided. Then, an upper metallization layer, which is arranged on the upper side and has a hardening area, is produced. In this case, at least one contiguous portion of the hardening area is created by at least part of the hardening material being diffused into the first metal foil.

摘要翻译： 本发明的一个方面涉及一种用于制造电路载体的方法。 为此，提供了一种电绝缘载体，其具有上侧以及与上侧相对的下侧。 同样提供第一金属箔和硬化材料。 然后，制造布置在上侧并具有硬化区域的上金属化层。 在这种情况下，硬化区域的至少一个连续部分由至少部分硬化材料扩散到第一金属箔中而产生。

公开(公告)号：US10092974B2

公开(公告)日：2018-10-09

申请号：US14751361

申请日：2015-06-26

申请人： Infineon Technologies AG

发明人： Mark Essert ,  Marianna Nomann ,  Thomas Nuebel ,  Guido Strotmann

IPC分类号： B23K20/00 ,  B23K20/10 ,  B23K20/22 ,  H05K3/32 ,  B23K101/38 ,  H05K1/02 ,  H05K1/03

摘要： One aspect of the invention relates to a method for producing a circuit carrier. For this purpose, an electrically insulating carrier is provided, having an upper side and also an underside opposite from the upper side. A first metal foil and a hardening material are likewise provided. Then, an upper metallization layer, which is arranged on the upper side and has a hardening area, is produced. In this case, at least one contiguous portion of the hardening area is created by at least part of the hardening material being diffused into the first metal foil.

公开(公告)号：US20240304538A1

公开(公告)日：2024-09-12

申请号：US18591580

申请日：2024-02-29

申请人： Infineon Technologies AG

发明人： Christoph Bayer ,  Matthias Bürger ,  Ulrich Nolten ,  Mark Essert

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L25/00 ,  H01L25/07

CPC分类号： H01L23/49844 ,  H01L23/14 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/181

摘要： A power semiconductor module arrangement includes: a substrate having a dielectric insulation layer and a first metallization layer arranged on a first surface of the dielectric insulation layer; at least one semiconductor body arranged on and attached to the first metallization layer by an electrically conductive connection layer; and at least one electrically conducting element arranged on the first metallization layer. The first metallization layer is a structured layer having a plurality of different sub-sections. The first metallization layer has a uniform thickness in a vertical direction, the vertical direction being perpendicular to the first surface of the dielectric insulation layer. Each electrically conducting element is arranged on and covers a subarea of a sub-section, thereby increasing a cross-sectional area of the subarea of the respective sub-section. Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body arranged thereon.

公开(公告)号：US09000580B2

公开(公告)日：2015-04-07

申请号：US13749884

申请日：2013-01-25

申请人： Infineon Technologies AG

发明人： Torsten Groening ,  Mark Essert ,  Christian Steininger ,  Roman Lennart Tschirbs

IPC分类号： H01L29/24 ,  H01L23/40 ,  H01L21/50 ,  H01L23/36 ,  H01L23/373 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/40 ,  H01L21/4878 ,  H01L21/50 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3735 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.

摘要翻译： 功率半导体模块包括具有顶面，下侧和形成在基板中的凹陷的基板。 凹陷延伸到从顶部进行的底板。 底板的厚度在凹陷区域局部减小。 功率半导体模块还包括布置在基板的顶侧上的凹陷上方的电路载体，使得凹陷插入电路载体和底板的下侧之间。