公开(公告)号：US20100129085A1

公开(公告)日：2010-05-27

申请号：US12697595

申请日：2010-02-01

Applicant: Igor I. Smolyaninov ,  Uzi Vishkin ,  Christopher C. Davis

Inventor： Igor I. Smolyaninov ,  Uzi Vishkin ,  Christopher C. Davis

IPC: H04B10/12

CPC classification number: G02B6/1226 ,  B82Y20/00

Abstract: Plasmonic systems and devices that utilize surface plasmon polaritons (or “plasmons”) for inter-chip and/or intra-chip communications are provided. A plasmonic system includes a microchip that has an integrated circuit module and a plasmonic device configured to interface with the integrated circuit module. The plasmonic device includes a first electrode, a second electrode positioned at a non-contact distance from the first electrode, and a tunneling-junction configured to create a plasmon when a potential difference is created between the first electrode and the second electrode.

Abstract translation: 提供了利用表面等离子体激元（或等离子体激元）进行芯片间和/或片内通信的等离子体系统和器件。 等离子体激元系统包括具有集成电路模块和配置成与集成电路模块接口的等离子体元件的微芯片。 等离子体元件装置包括第一电极，位于与第一电极非接触距离的第二电极以及当在第一电极和第二电极之间产生电位差时构造成产生等离子体激元的隧道结。

公开(公告)号：US20070223940A1

公开(公告)日：2007-09-27

申请号：US11646734

申请日：2006-12-28

Applicant: Igor I. Smolyaninov ,  Uzi Vishkin ,  Christopher C. Davis

Inventor： Igor I. Smolyaninov ,  Uzi Vishkin ,  Christopher C. Davis

IPC: H04B10/06

CPC classification number: G02B6/1226 ,  B82Y20/00

Abstract: Plasmonic systems and devices that utilize surface plasmon polaritons (or “plasmons”) for inter-chip and/or intra-chip communications are provided. A plasmonic system includes a microchip that has an integrated circuit module and a plasmonic device configured to interface with the integrated circuit module. The plasmonic device includes a first electrode, a second electrode positioned at a non-contact distance from the first electrode, and a tunneling-junction configured to create a plasmon when a potential difference is created between the first electrode and the second electrode.

Abstract translation: 提供了利用表面等离子体激元（或等离子体激元）进行芯片间和/或片内通信的等离子体系统和器件。 等离子体激元系统包括具有集成电路模块和配置成与集成电路模块接口的等离子体元件的微芯片。 等离子体元件装置包括第一电极，位于与第一电极非接触距离的第二电极以及当在第一电极和第二电极之间产生电位差时构造成产生等离子体激元的隧道结。

公开(公告)号：US20090119481A1

公开(公告)日：2009-05-07

申请号：US11606860

申请日：2006-11-29

Applicant: Uzi Vishkin

Inventor： Uzi Vishkin

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/383 ,  G06F9/3851

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory.

Abstract translation: 在一个实施例中，串行处理器被配置为以串行方式在软件程序中执行软件指令。 串行存储器被配置为存储串行处理器在串行执行软件指令时使用的数据。 多个并行处理器被配置为并行地在软件程序中执行软件指令。 多个分区存储器模块被提供和配置为存储数据供多个并行处理器并行执行软件指令使用。 因此，提供了一种处理器/存储器结构，其允许串行程序使用快速本地串行存储器和并行程序来使用分割的并行存储器。 系统可以在串行模式和并行模式之间切换。 该系统可以包含几个品种的预取命令。 例如，为了在串行模式和并行模式之间切换，串行处理器被配置为发送信号以开始从共享存储器预取数据。

公开(公告)号：US20060051101A1

公开(公告)日：2006-03-09

申请号：US10529310

申请日：2004-03-17

Applicant: Uzi Vishkin

Inventor： Uzi Vishkin

IPC: H04B10/00

CPC classification number: G06F13/409 ,  G02B6/43 ,  G06F12/0813 ,  H04B10/801

Abstract: A multi-chip processor/memory arrangement replacing a large computer chip, includes a number of modules each including processing elements, registers, and/or memories interconnected by an optical interconnection fabric providing an all-to-all interconnection between the chips, so that the memory cells on each chip represent a portion of shared memory. The optical interconnect fabric is responsible for transporting data between the chips while processing elements on each chip dominate processing. Each chip is manufactured in mass production so that the entire processor/memory arrangement is fabricated in an inexpensive and simplified technology process. The optical communication fabric is based on waveguide technology and includes a number of waveguides, the layout of which follows certain constraints. The waveguides can intersect each other in the single plane, or alternatively, a double layer of waveguide structures and bent over approach may be used. Specific layout patterns of the optical waveguides are presented. The communication of data along the optical communication channels is performed in highly pipelined decentralized routing manner and is envisioned for XMT architecture application.

公开(公告)号：US07505822B2

公开(公告)日：2009-03-17

申请号：US10529310

申请日：2004-03-17

Applicant: Uzi Vishkin

Inventor： Uzi Vishkin

IPC: G06F19/00

CPC classification number: G06F13/409 ,  G02B6/43 ,  G06F12/0813 ,  H04B10/801

Abstract: A multi-chip processor/memory arrangement replacing a large computer chip, includes a number of modules each including processing elements, registers, and/or memories interconnected by an optical interconnection fabric providing an all-to-all interconnection between the chips, so that the memory cells on each chip represent a portion of shared memory. The optical interconnect fabric is responsible for transporting data between the chips while processing elements on each chip dominate processing. Each chip is manufactured in mass production so that the entire processor/memory arrangement is fabricated in an inexpensive and simplified technology process. The optical communication fabric is based on waveguide technology and includes a number of waveguides, the layout of which follows certain constraints. The waveguides can intersect each other in the single plane, or alternatively, a double layer of waveguide structures and bent over approach may be used. Specific layout patterns of the optical waveguides are presented. The communication of data along the optical communication channels is performed in highly pipelined decentralized routing manner and is envisioned for XMT architecture application.

Abstract translation: 代替大型计算机芯片的多芯片处理器/存储器装置包括多个模块，每个模块包括通过提供芯片之间的所有互连的光互连结构互连的处理元件，寄存器和/或存储器，从而 每个芯片上的存储单元表示共享存储器的一部分。 光学互连结构负责在芯片之间传输数据，同时处理每个芯片上的元件主导处理。 每个芯片都是批量生产的，因此整个处理器/存储器装置是以廉价和简化的工艺流程制造的。 光通信结构基于波导技术，并且包括多个波导，其布局遵循某些约束。 波导可以在单个平面中彼此相交，或者可以使用双层波导结构和弯曲方法。 介绍了光波导的具体布局模式。 沿着光通信信道的数据通信以高度流水线分散的路由方式执行，并且被设想用于XMT架构应用。

公开(公告)号：US06542918B1

公开(公告)日：2003-04-01

申请号：US09224104

申请日：1998-12-31

Applicant: Uzi Vishkin

Inventor： Uzi Vishkin

IPC: G06F750

CPC classification number: G06F7/506 ,  G06F9/3001 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3885 ,  G06F9/3893 ,  G06F2207/5063

Abstract: A method for performing prefix sums, by including a prefix sum instruction in the instruction set of a microprocessor. Both general prefix summation, base-zero prefix summation and base-zero suffix summation are included in the scope of the present invention. The prefix sum instruction may be implemented in software, using the instructions of existing instruction sets, or may be implemented in dedicated hardware, for example, as a functional unit of a microprocessor. The hardware implementation is suitable for application to the allocation of computational resources among concurrent tasks. The scope of the present invention includes one such application: guaranteeing conflict-free access to multiple single-ported register files.

Abstract translation: 一种用于通过在微处理器的指令集中包括前缀和指令来执行前缀和的方法。 通用前缀求和，基零前缀求和和基零后缀求和都包含在本发明的范围内。 前缀和指令可以使用现有指令集的指令在软件中实现，或者可以在专用硬件中实现，例如作为微处理器的功能单元。 硬件实现适用于并发任务中计算资源的分配。 本发明的范围包括一个这样的应用：保证对多个单端口寄存器文件的无冲突访问。

公开(公告)号：US07707388B2

公开(公告)日：2010-04-27

申请号：US11606860

申请日：2006-11-29

Applicant: Uzi Vishkin

Inventor： Uzi Vishkin

IPC: G06F15/76

CPC classification number: G06F9/383 ,  G06F9/3851

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory.

Abstract translation: 在一个实施例中，串行处理器被配置为以串行方式在软件程序中执行软件指令。 串行存储器被配置为存储串行处理器在串行执行软件指令时使用的数据。 多个并行处理器被配置为并行地在软件程序中执行软件指令。 多个分区存储器模块被提供和配置为存储数据供多个并行处理器并行执行软件指令使用。 因此，提供了一种处理器/存储器结构，其允许串行程序使用快速本地串行存储器和并行程序来使用分割的并行存储器。 系统可以在串行模式和并行模式之间切换。 该系统可以包含几个品种的预取命令。 例如，为了在串行模式和并行模式之间切换，串行处理器被配置为发送信号以开始从共享存储器预取数据。