公开(公告)号：US20040110354A1

公开(公告)日：2004-06-10

申请号：US10316211

申请日：2002-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

IPC: H01L021/331 ,  H01L021/8222

CPC classification number: H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

Abstract: An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Abstract translation: 描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。 所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。 绝缘TEOS玻璃提供降低的电容并有助于实现高速度。 还描述了用于实施所公开的方法的装置。

公开(公告)号：US20040097047A1

公开(公告)日：2004-05-20

申请号：US10300239

申请日：2002-11-20

Applicant: International Business Machines Corporation

Inventor： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC: H01L021/336

CPC classification number: H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

Abstract: A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

Abstract translation: 一种用于制造FET器件的工艺。 半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。 可以加入氧化硅的毯层。 可以在栅电极周围的氧化硅层上形成可选的氮化硅环。 执行两个预清洗步骤。 然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。 由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。 一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

公开(公告)号：US20040014271A1

公开(公告)日：2004-01-22

申请号：US10064476

申请日：2002-07-18

Applicant: International Business Machines Corporation

Inventor： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC: H01L021/8238 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

Abstract translation: 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。 优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。 掺杂剂的这种扩散形成至少一部分外在碱。 特别地，通过扩散形成与本征基区相邻的部分。 该解决方案避免了植入外在基础的传统解决方案所引起的问题。 具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。 这种降低的损伤增强了掺杂剂扩散到本征基质中。 另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。 另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

公开(公告)号：US20010001298A1

公开(公告)日：2001-05-17

申请号：US09748965

申请日：2000-12-27

Applicant: International Business Machines Corporation

Inventor： Marc W. Cantell ,  Jerome B. Lasky ,  Ronald J. Line ,  William J. Murphy ,  Kirk D. Peterson ,  Prabhat Tiwari

IPC: H01L021/44

CPC classification number: H01L21/28518 ,  Y10S414/139 ,  Y10S438/906 ,  Y10S438/908

Abstract: A method and apparatus are provided for forming a silicide on a semiconductor substrate by integrating under a constant vacuum the processes of removing an oxide from a surface of a semiconductor substrate and depositing a metal on the cleaned surface without exposing the cleaned surface to air. The method and apparatus of the present invention eliminates the exposure of the cleaned substrate to air between the oxide removal and metal deposition steps. This in-situ cleaning of the silicon substrate prior to cobalt deposition provides a cleaner silicon substrate surface, resulting in enhanced formation of cobalt silicide when the cobalt layer is annealed.

Abstract translation: 提供一种方法和装置，用于通过在恒定真空下整合从半导体衬底的表面去除氧化物并在清洁的表面上沉积金属而不将清洁的表面暴露于空气的过程来在半导体衬底上形成硅化物。 本发明的方法和装置消除了在氧化物去除和金属沉积步骤之间清洁的衬底对空气的暴露。 在钴沉积之前对硅衬底的原位清洁提供了更清洁的硅衬底表面，当钴层退火时，导致硅化钴的形成增强。