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1.发明公开公开(公告)号：US20240094999A1
公开(公告)日：2024-03-21
申请号：US17948425
申请日：2022-09-20
发明人： Kazuaki Ishizaki
CPC分类号： G06F8/4441 , G06F9/3887
摘要： A computer-implemented method, system and computer program product for improving the performance of a program that manipulates two vectors of data. It is determined whether the program contains one of the following patterns: a first pattern corresponding to v0.rearrange(s, v1); a second pattern corresponding to v0.blend(v1, m); and a third pattern corresponding to v0.rearrange(s).blend(v1.rearrange(s), m). Upon identifying code written as the first pattern in the program, the first pattern is rewritten and replaced with the second or third pattern if the execution time of the program with the second or third pattern is less than the execution time of the program with the first program. In a similar manner, upon identifying code written as the second or third pattern in the program, the second or third pattern is rewritten and replaced with the first pattern if the execution time of the program can be improved.
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公开(公告)号：US20180321916A1
公开(公告)日：2018-11-08
申请号：US15584432
申请日：2017-05-02
CPC分类号： G06F8/30 , G06F8/52 , G06F9/45504
摘要： A method includes identifying a code portion that accesses a primitive value in a user-defined function included in a user program, converting the code portion and an argument in a manner to directly reference an internal data representation of the user program, and generating a code for calling the user-defined function converted by the conversion.
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公开(公告)号：US20180203783A1
公开(公告)日：2018-07-19
申请号：US15409241
申请日：2017-01-18
发明人： Kazuaki Ishizaki
CPC分类号： G06F11/3409 , G06F9/44505 , G06F9/45516 , G06F11/3024
摘要： A method for improving performance of a system including a first processor and a second processor includes obtaining a code region specified to be executed on the second processor, the code region including a plurality of instructions, calculating a performance improvement of executing at least one of the plurality of instructions included in the code region on the second processor over executing the at least one instruction on the first processor, removing the at least one instruction from the code region in response to a condition including that the performance improvement does not exceed a first threshold, and repeating the calculating and the removing to produce a modified code region specified to be executed on the second processor.
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4.发明申请公开(公告)号：US20170124677A1
公开(公告)日：2017-05-04
申请号：US14931096
申请日：2015-11-03
发明人： Kazuaki Ishizaki
摘要： A method is provided for buffer allocation on a graphics processing unit. The method includes analyzing, by the graphics processing unit, a program to be executed on the graphics processing unit to determine, for an object in the program, a set of elements in the object that are designated to be accessed during an execution of the program. The method further includes allocating, by the graphics processing unit, a placement of the object in a device buffer on the graphics processing unit based on the set of elements to minimize a number of memory accesses during the execution of the program.
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公开(公告)号：US20150026433A1
公开(公告)日：2015-01-22
申请号：US14321852
申请日：2014-07-02
发明人： Kazuaki Ishizaki
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3012
摘要： An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
摘要翻译： 一种用于在具有一个或多个映射表的系统中分配架构寄存器的分配系统和方法。 当分配系统向分配目标虚拟寄存器检测到多个可用架构寄存器时，它识别具有其目的地操作数中的分配目标虚拟寄存器的所有指令的相邻指令，对目的地操作数中出现的架构寄存器的使用次数进行计数 对于每个架构寄存器，将具有与架构寄存器相关的相同分配规则的一个或多个映射表中的每个条目组的每个结构寄存器的使用次数相加，计算每个条目组的条目的使用数量的总和 ，并将架构寄存器分配给分配目标虚拟寄存器，使得每个入口组的条目的使用数量的总和接近均匀。
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公开(公告)号：US20190220258A1
公开(公告)日：2019-07-18
申请号：US15872534
申请日：2018-01-16
发明人： Kazuaki Ishizaki
摘要： A computer-implemented method and a computer program product are provided for converting a first object having a first data format to a second object having a second data format that is different from the first format in that the second data format requires an object header. The method includes adding the object header to the first object. The method further includes returning, as a pointer, an address of the added object header to a user defined function that uses the second object. The first object lacks pointers to other objects, and does not escape.
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7.发明申请公开(公告)号：US20180253290A1
公开(公告)日：2018-09-06
申请号：US15808615
申请日：2017-11-09
发明人： Kazuaki Ishizaki
IPC分类号： G06F9/45
CPC分类号： G06F8/452 , G06F8/20 , G06F8/433 , G06F8/4442 , G06F8/447 , G06F8/45 , G06F8/453 , G06F8/456 , G06F9/4552
摘要： Computer-implemented methods are provided for compiling a parallel loop and generating Graphics Processing Unit (GPU) code and Central Processing Unit (CPU) code for writing an array for the GPU and the CPU. A method includes compiling the parallel loop by (i) checking, based on a range of array elements to be written, whether the parallel loop can update all of the array elements and (ii) checking whether an access order of the array elements that the parallel loop reads or writes is known at compilation time. The method further includes determining an approach, from among a plurality of available approaches, to generate the CPU code and the GPU code based on (i) the range of the array elements to be written and (ii) the access order to the array elements in the parallel loop.
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8.发明申请公开(公告)号：US20170256028A1
公开(公告)日：2017-09-07
申请号：US15604553
申请日：2017-05-24
发明人： Kazuaki Ishizaki
IPC分类号： G06T1/60 , G06F12/0875
CPC分类号： G06T1/60 , G06F12/0875 , G06F2212/452 , G06F2212/455
摘要： A method and system are provided for executing, by a processor including a read-only cache, a program having a plurality of variables including a first variable and a second variable. Each variable is for executing a respective read operation or a respective write operation for an object. The method includes providing a first code that uses the read-only cache and a second code that does not use the read-only cache. The method further includes determining, by the processor, whether a first object designated by the first variable is aliased or not aliased with a second object designated by the second variable. The method also includes executing, by the processor, the first code when the first object is not aliased with the second object, and the second code when the first object is aliased with the second object.
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9.发明申请ALLOCATION METHOD, APPARATUS, AND PROGRAM FOR MANAGING ARCHITECTURAL REGISTERS AND PHYSICAL REGISTERS USING MAPPING TABLES 有权用于管理建筑物登记的配置方法，装置和程序以及使用映射表的物理寄存器公开(公告)号：US20170024214A1
公开(公告)日：2017-01-26
申请号：US15285909
申请日：2016-10-05
发明人： Kazuaki Ishizaki
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3012
摘要： An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
摘要翻译： 一种用于在具有一个或多个映射表的系统中分配架构寄存器的分配系统和方法。 当分配系统向分配目标虚拟寄存器检测到多个可用架构寄存器时，它识别具有其目的地操作数中的分配目标虚拟寄存器的所有指令的相邻指令，对目的地操作数中出现的架构寄存器的使用次数进行计数 对于每个架构寄存器，将具有与架构寄存器相关的相同分配规则的一个或多个映射表中的每个条目组的每个结构寄存器的使用次数相加，计算每个条目组的条目的使用数量的总和 ，并将架构寄存器分配给分配目标虚拟寄存器，使得每个入口组的条目的使用数量的总和接近均匀。
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10.发明授权Allocation method, apparatus, and program for managing architectural registers and physical registers using mapping tables 有权使用映射表管理架构寄存器和物理寄存器的分配方法，设备和程序公开(公告)号：US09542185B2
公开(公告)日：2017-01-10
申请号：US14321852
申请日：2014-07-02
发明人： Kazuaki Ishizaki
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3012
摘要： An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
摘要翻译： 一种用于在具有一个或多个映射表的系统中分配架构寄存器的分配系统和方法。 当分配系统向分配目标虚拟寄存器检测到多个可用架构寄存器时，它识别具有其目的地操作数中的分配目标虚拟寄存器的所有指令的相邻指令，对目的地操作数中出现的架构寄存器的使用次数进行计数 对于每个架构寄存器，将具有与架构寄存器相关的相同分配规则的一个或多个映射表中的每个条目组的每个结构寄存器的使用次数相加，计算每个条目组的条目的使用数量的总和 ，并将架构寄存器分配给分配目标虚拟寄存器，使得每个入口组的条目的使用数量的总和接近均匀。
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