公开(公告)号：US11561900B1

公开(公告)日：2023-01-24

申请号：US17394153

申请日：2021-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bernard C. Drerup ,  Guy L. Guthrie ,  Jeffrey A. Stuecheli ,  Alexander Michael Taft ,  Derek E. Williams

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/0888

Abstract: A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.

公开(公告)号：US20230078861A1

公开(公告)日：2023-03-16

申请号：US17447759

申请日：2021-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bernard C. Drerup ,  Guy L. Guthrie ,  Joseph John McGill, IV ,  Alexander Michael Taft ,  Derek E. Williams

IPC: G06F9/4401 ,  G06F12/0842 ,  G06F13/28

Abstract: The present disclosure may include a processor that uses idle caches as a backing store for a boot code. The processor designates a boot core and an active cache from a plurality of cores and a plurality of caches. The processor configures remaining caches from the plurality of caches to act as a backing store memory. The processor modifies the active cache to convert cast outs to a system memory into lateral cast outs to the backing store memory. The processor copies a boot image to the backing store memory and executes the boot image by the boot core.

公开(公告)号：US20230041702A1

公开(公告)日：2023-02-09

申请号：US17394173

申请日：2021-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DEREK E. WILLIAMS ,  GUY L. GUTHRIE ,  Bernard C. Drerup ,  Hugh Shen ,  Alexander Michael Taft ,  Luke Murray ,  Richard Nicholas

IPC: G06F12/0811 ,  G06F12/121 ,  G06F30/32

Abstract: A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

公开(公告)号：US11561901B1

公开(公告)日：2023-01-24

申请号：US17394173

申请日：2021-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Bernard C. Drerup ,  Hugh Shen ,  Alexander Michael Taft ,  Luke Murray ,  Richard Nicholas

IPC: G06F12/0811 ,  G06F30/32 ,  G06F12/121

Abstract: A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

公开(公告)号：US11635968B2

公开(公告)日：2023-04-25

申请号：US17447759

申请日：2021-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bernard C. Drerup ,  Guy L. Guthrie ,  Joseph John McGill, IV ,  Alexander Michael Taft ,  Derek E. Williams

IPC: G06F9/4401 ,  G06F13/28 ,  G06F12/0842 ,  G06F9/445 ,  G06F12/0897

Abstract: The present disclosure may include a processor that uses idle caches as a backing store for a boot code. The processor designates a boot core and an active cache from a plurality of cores and a plurality of caches. The processor configures remaining caches from the plurality of caches to act as a backing store memory. The processor modifies the active cache to convert cast outs to a system memory into lateral cast outs to the backing store memory. The processor copies a boot image to the backing store memory and executes the boot image by the boot core.

公开(公告)号：US11573902B1

公开(公告)日：2023-02-07

申请号：US17405713

申请日：2021-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hugh Shen ,  Guy L. Guthrie ,  Jeffrey A. Stuecheli ,  Luke Murray ,  Alexander Michael Taft ,  Bernard C. Drerup ,  Derek E. Williams

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/0817

Abstract: A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.

公开(公告)号：US11556472B1

公开(公告)日：2023-01-17

申请号：US17394195

申请日：2021-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Alexander Michael Taft ,  Guy L. Guthrie ,  Bernard C. Drerup

IPC: G06F12/08 ,  G06F12/0831 ,  G06F9/30 ,  G06F12/0817

Abstract: A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.