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公开(公告)号：US3599160A
公开(公告)日：1971-08-10
申请号：US3599160D
申请日：1969-03-06
Applicant: INTERDATA INC
Inventor： NESTLE ELLIOT , SCHUNNEMAN ROBERT F
Abstract: Digital time division multiplexing system and method for multiplexing and demultiplexing between serial data from a plurality of data lines and data in the form of parallel characters. Individual data line units are operable for loading and unloading data and a multiplexor control unit controls in sequence groups of the data line units. A processor controls input serial data flow from each data line unit through a buss and the processor into core memory. A fixed wired program has logic connections to the processor, core memory, multiplexor control unit and clock and has fixed program instruction blocks to control the operation of the multiplexor control unit, to determine the start of a character and to then control the strobing of the input serial data in the core memory.
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公开(公告)号：US3646522A
公开(公告)日：1972-02-29
申请号：US3646522D
申请日：1969-08-15
Applicant: INTERDATA INC
Inventor： FURMAN ARTHUR R , JONES RICHARD , MORELAND CHARLES , NESTLE ELLIOT
CPC classification number: G06F7/5272 , G06F7/535 , G06F9/226 , G06F9/261 , G06F2207/5353
Abstract: A processor system having a main memory to store user instructions and a read only memory which contains microroutines to emulate the user instructions. A user''s instruction is fetched from the main memory and placed in an instruction register, a separate decode read only memory holds the individual starting address for the appropriate microroutine utilized in a current user instruction. The operation code of the user''s instruction is applied from the instruction register to the decode read only memory for obtaining the starting address of a predetermined microroutine. Further, multiplication and division are performed according to a unique set of microroutines to significantly decrease processor operating time.
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