A processor system having a main memory to store user instructions and a read only memory which contains microroutines to emulate the user instructions. A user''s instruction is fetched from the main memory and placed in an instruction register, a separate decode read only memory holds the individual starting address for the appropriate microroutine utilized in a current user instruction. The operation code of the user''s instruction is applied from the instruction register to the decode read only memory for obtaining the starting address of a predetermined microroutine. Further, multiplication and division are performed according to a unique set of microroutines to significantly decrease processor operating time.