公开(公告)号：US20240256825A1

公开(公告)日：2024-08-01

申请号：US18435528

申请日：2024-02-07

申请人： Intel Corporation

发明人： Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Ben J. Ashbaugh ,  Jingyi Jin ,  Jeremy Bottleson ,  Mike B. Macpherson ,  Kevin Nealis ,  Dhawal Srivastava ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Altug Koker ,  Abhishek R. Appu

IPC分类号： G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20

CPC分类号： G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

摘要： A library of machine learning primitives is provided to optimize a machine learning model to improve the efficiency of inference operations. In one embodiment a trained convolutional neural network (CNN) model is processed into a trained CNN model via pruning, convolution window optimization, and quantization.

公开(公告)号：US11748606B2

公开(公告)日：2023-09-05

申请号：US17317857

申请日：2021-05-11

申请人： INTEL CORPORATION

发明人： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC分类号： G06F7/50 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20 ,  G06F9/30 ,  G06T15/00 ,  G06F15/78 ,  G06F15/76 ,  G06F1/3287 ,  G06F1/3293 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06T1/60

CPC分类号： G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/76 ,  G06F15/78 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06T1/20 ,  G06T15/005 ,  G06T1/60

摘要： In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220357945A1

公开(公告)日：2022-11-10

申请号：US17834482

申请日：2022-06-07

申请人： Intel Corporation

发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC分类号： G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

公开(公告)号：US20220261948A1

公开(公告)日：2022-08-18

申请号：US17684187

申请日：2022-03-01

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC分类号： G06T1/20 ,  G06F3/14 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T15/00 ,  G09G5/36

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

公开(公告)号：US20220245753A1

公开(公告)日：2022-08-04

申请号：US17720804

申请日：2022-04-14

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00

摘要： Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple or mixed precisions and dynamic ranges.

公开(公告)号：US11308574B2

公开(公告)日：2022-04-19

申请号：US16983080

申请日：2020-08-03

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06T15/00

摘要： Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US20190146800A1

公开(公告)日：2019-05-16

申请号：US16227645

申请日：2018-12-20

申请人： Intel Corporation

发明人： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC分类号： G06F9/38 ,  G06N20/00 ,  G06F15/80 ,  G06F13/42 ,  G06F9/30 ,  G06F13/40 ,  G06T1/20 ,  G06N3/00 ,  G06F9/50

摘要： One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

公开(公告)号：US20180315157A1

公开(公告)日：2018-11-01

申请号：US15581167

申请日：2017-04-28

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben . Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06F7/483 ,  G06N99/00

摘要： One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

公开(公告)号：US20180307971A1

公开(公告)日：2018-10-25

申请号：US15495020

申请日：2017-04-24

申请人： Intel Corporation

发明人： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20

CPC分类号： G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/78 ,  G06N3/04 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

摘要： In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180307495A1

公开(公告)日：2018-10-25

申请号：US15819167

申请日：2017-11-21

申请人： Intel Corporation

发明人： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC分类号： G06F9/38 ,  G06N99/00 ,  G06F13/40 ,  G06F13/42 ,  G06F9/30

CPC分类号： G06F9/3887 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06F2213/0026 ,  G06N3/00 ,  G06N99/005 ,  G06T1/20

摘要： One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.