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公开(公告)号：US20240172450A1
公开(公告)日：2024-05-23
申请号：US18421986
申请日：2024-01-25
发明人： Weiliang Jing , Kailiang Huang , Junxiao Feng , Zhengbo Wang
CPC分类号： H10B53/30 , H01L29/40111 , H01L29/42392 , H10B53/10 , H10B53/20 , H10B53/40
摘要： A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.
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公开(公告)号：US20240331739A1
公开(公告)日：2024-10-03
申请号：US18741084
申请日：2024-06-12
发明人： Jincan Guo , Tianqiang Huang , Rongbin Liu , Jieqiang Chen , Yun Liu , Zhengbo Wang
CPC分类号： G11C5/063 , G11C7/1048
摘要： This disclosure discloses a memory, a memory use method, a memory manufacturing method, and an electronic device. The memory includes a control layer and at least one storage layer stacked on the control layer. The storage layer includes a plurality of storage channels, and each storage channel includes an independent data interface bus. The control layer includes a plurality of controllers and a plurality of user interfaces, the controller is configured to access data stored in a storage channel connected to the controller. The plurality of controllers are connected to the data interface buses of the plurality of storage channels in one-to-one correspondence. A quantity of user interfaces is the same as a quantity of user storage channels that can be invoked by a user. The quantity of user interfaces is less than a quantity of controllers.
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公开(公告)号：US20230315566A1
公开(公告)日：2023-10-05
申请号：US18331635
申请日：2023-06-08
发明人： Guoming Shen , Zhengbo Wang , Xuewen Yi
IPC分类号： G06F11/10
CPC分类号： G06F11/1044
摘要： A storage apparatus includes a first memory disposed in a first die and configured to store data, a second memory disposed in a second die and configured to store an error correcting code corresponding to the data. The error correcting code may be used to perform data protection on the data. A storage controller is configured to write the data into the first memory, and read the data from the first memory.
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公开(公告)号：US12014058B2
公开(公告)日：2024-06-18
申请号：US18146996
申请日：2022-12-27
发明人： Weiliang Jing , Zhengbo Wang , Jingjie Cui
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0685 , G11C5/025 , G11C5/04 , G11C5/063
摘要： A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.
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5.发明公开公开(公告)号：US20230371229A1
公开(公告)日：2023-11-16
申请号：US18358434
申请日：2023-07-25
发明人： Weiliang Jing , Kailiang Huang , Junxiao Feng , Zhengbo Wang
IPC分类号： H10B12/00
CPC分类号： H10B12/00
摘要： A thin-film transistor (TFT) includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate.
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公开(公告)号：US20240121942A1
公开(公告)日：2024-04-11
申请号：US18542615
申请日：2023-12-16
发明人： Weiliang Jing , Kailiang Huang , Junxiao Feng , Zhengbo Wang
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/0335 , H10B12/482 , H10B12/488
摘要： A memory comprises a substrate and a plurality of storage units formed on the substrate. Each of the storage units includes a transistor and a capacitor electrically connected to the transistor. The transistor includes a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer. The first electrode and the second electrode are arranged in a first direction. The gate is located between the first electrode and the second electrode. The semiconductor layer is located on one of two opposite sides of the gate in a second direction. The semiconductor layer is electrically connected separately to the first electrode and the second electrode, the gate and the semiconductor layer are isolated from each other by the gate dielectric layer, and the second direction is a direction parallel to the substrate.
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公开(公告)号：US11809730B2
公开(公告)日：2023-11-07
申请号：US17389461
申请日：2021-07-30
发明人： Xianfu Zhang , Zhengbo Wang
CPC分类号： G06F3/0647 , G06F3/0604 , G06F3/0653 , G06F3/0673
摘要： A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.
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公开(公告)号：US20230139599A1
公开(公告)日：2023-05-04
申请号：US18146996
申请日：2022-12-27
发明人： Weiliang Jing , Zhengbo Wang , Jingjie Cui
IPC分类号： G06F3/06
摘要： A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.
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