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Patent Agency Ranking
公开(公告)号：US20200249909A1
公开(公告)日：2020-08-06
申请号：US16264070
申请日：2019-01-31
Inventor： Hing-Mo Lam , Man-Wai Kwan , Ching-Hong Leung , Kong-Chau Tsang
Abstract: Systems and methods that provide reconfigurable shifter configurations supporting multiple instruction, multiple data (MIMD) are described. Shifters implemented according to embodiments support multiple data shifts with respect to an instance of data shifting, wherein multiple individual different data shifts are implemented at a time in parallel. Reconfigurable segmented scalable shifters of embodiments, in addition being reconfigurable for scalability in supporting data shifting with respect to various bit lengths of data, are configured to support data shifting of differing bit lengths in parallel. The data shifters of embodiments implement segmentation for facilitating data shifting with respect to differing bit lengths. Different data shift commands may be provided with respect to each such segment, thereby facilitating multiple data shifts in parallel with respect to various bit lengths of data. Reconfigurable segmented scalable shifter configurations provide for fully reconfigurable data width and shift command of each message of input data.
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公开(公告)号：US10826529B2
公开(公告)日：2020-11-03
申请号：US16264161
申请日：2019-01-31
Inventor： Hing-Mo Lam , Syed Mohsin Abbas , Zhuohan Yang , Zhonghui Zhang , Man-Wai Kwan , Ching-Hong Leung , Kong-Chau Tsang
IPC: H03M13/11
Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.
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公开(公告)号：US20230006694A1
公开(公告)日：2023-01-05
申请号：US17367195
申请日：2021-07-02
Inventor： Hing-Mo Lam , Hin-Tat Chan , Ying-Lun Tsue , Zhonghui Zhang , Man-Wai Kwan , Kong-Chau Tsang
Abstract: Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.
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公开(公告)号：US11575390B2
公开(公告)日：2023-02-07
申请号：US17367195
申请日：2021-07-02
Inventor： Hing-Mo Lam , Hin-Tat Chan , Ying-Lun Tsui , Zhonghui Zhang , Man-Wai Kwan , Kong-Chau Tsang
Abstract: Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.
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公开(公告)号：US20200252080A1
公开(公告)日：2020-08-06
申请号：US16264161
申请日：2019-01-31
Inventor： Hing-Mo Lam , Syed Mohsin Abbas , Zhuohan Yang , Zhonghui Zhang , Man-Wai Kwan , Ching-Hong Leung , Kong-Chau Tsang
IPC: H03M13/11
Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.
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