公开(公告)号：US10826529B2

公开(公告)日：2020-11-03

申请号：US16264161

申请日：2019-01-31

Applicant: Hong Kong Applied Science and Technology Research Institute Co., Ltd.

Inventor： Hing-Mo Lam ,  Syed Mohsin Abbas ,  Zhuohan Yang ,  Zhonghui Zhang ,  Man-Wai Kwan ,  Ching-Hong Leung ,  Kong-Chau Tsang

IPC: H03M13/11

Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.

公开(公告)号：US20200252080A1

公开(公告)日：2020-08-06

申请号：US16264161

申请日：2019-01-31

Applicant: Hong Kong Applied Science and Technology Research Institute Co., Ltd.

Inventor： Hing-Mo Lam ,  Syed Mohsin Abbas ,  Zhuohan Yang ,  Zhonghui Zhang ,  Man-Wai Kwan ,  Ching-Hong Leung ,  Kong-Chau Tsang

IPC: H03M13/11

Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.