公开(公告)号：US20110272740A1

公开(公告)日：2011-11-10

申请号：US13185818

申请日：2011-07-19

Applicant: Hidekazu UMEDA ,  Masahiro HIKITA ,  Tetsuzo UEDA

Inventor： Hidekazu UMEDA ,  Masahiro HIKITA ,  Tetsuzo UEDA

IPC: H01L29/80 ,  H01L21/335

CPC classification number: H01L29/7783 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

Abstract translation: 场效应晶体管包括形成在衬底上的第一半导体层和第二半导体层。 第一半导体层具有设置为包含非导电杂质的隔离区域的含有区域和不含非导电杂质的非含有区域。 第一区域由容纳区域和非含有区域之间的界面的一部分的附近限定，界面的部分在栅电极下方，包括界面部分的附近包含在包含 地区。 第二半导体层包括位于第一区域正上方的第二区域。 第二区域的非导电杂质的浓度低于第一区域的浓度。

公开(公告)号：US20080149965A1

公开(公告)日：2008-06-26

申请号：US11939899

申请日：2007-11-14

Applicant: Kazuhiro KAIBARA ,  Masahiro HIKITA ,  Tetsuzo UEDA ,  Yasuhiro UEMOTO ,  Tsuyoshi TANAKA

Inventor： Kazuhiro KAIBARA ,  Masahiro HIKITA ,  Tetsuzo UEDA ,  Yasuhiro UEMOTO ,  Tsuyoshi TANAKA

IPC: H01L29/80 ,  H01L21/335

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/432

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract translation: 晶体管包括：第一半导体层和具有第一区域和第二区域的第二半导体层，其顺序地形成在衬底上; 形成在除了第一和第二区域之外的第二半导体层的区域上的第一p型半导体层; 以及形成在第一p型半导体层上的第二p型半导体层。 第一p型半导体层与漏电极分离，其间具有由第一区域构成的底部的第一沟槽和源极电极之间插入具有由第二区域构成的底部的第二沟槽。

公开(公告)号：US20110114967A1

公开(公告)日：2011-05-19

申请号：US13010238

申请日：2011-01-20

Applicant: Masahiro HIKITA ,  Tetsuzo UEDA ,  Manabu YANAGIHARA ,  Yasuhiro UEMOTO ,  Tsuyoshi TANAKA

Inventor： Masahiro HIKITA ,  Tetsuzo UEDA ,  Manabu YANAGIHARA ,  Yasuhiro UEMOTO ,  Tsuyoshi TANAKA

IPC: H01L29/205 ,  H01L29/78

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

Abstract translation: 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅电极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

公开(公告)号：US20110037100A1

公开(公告)日：2011-02-17

申请号：US12912346

申请日：2010-10-26

Applicant: Masahiro HIKITA ,  Tetsuzo UEDA

Inventor： Masahiro HIKITA ,  Tetsuzo UEDA

IPC: H01L29/737

CPC classification number: H01L29/2003 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/808

Abstract: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.

Abstract translation: 氮化物半导体器件包括：顺序地在衬底上形成的第一至第三氮化物半导体层。 第二氮化物半导体层的带隙能量大于第一氮化物半导体层的带隙能量。 第三氮化物半导体层具有开口。 形成p型第四氮化物半导体层，使得开口被填充。 在第四氮化物半导体层上形成栅电极。

公开(公告)号：US20110227093A1

公开(公告)日：2011-09-22

申请号：US13150574

申请日：2011-06-01

Applicant: Masahiro HIKITA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

Inventor： Masahiro HIKITA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

IPC: H01L29/20 ,  H01L21/337 ,  H01L29/808

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/808

Abstract: The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.

Abstract translation: 本发明的目的是提供一种能够增加阈值电压以及降低导通电阻的FET和FET的制造方法。 本发明的FET包括第一未掺杂的GaN层; 形成在第一未掺杂的GaN层上的第一未掺杂的AlGaN层，其带隙能量大于第一未掺杂的GaN层的带隙能量; 形成在第一未掺杂的AlGaN层上的第二未掺杂的GaN层; 形成在所述第二未掺杂GaN层上的第二未掺杂AlGaN层，具有大于所述第二未掺杂GaN层的带隙能量的带隙能量; 形成在第二未掺杂AlGaN层的凹部中的p型GaN层; 形成在p型GaN层上的栅电极; 以及形成在所述栅电极的两个横向区域中的源电极和漏电极，其中在所述第一未掺杂的GaN层和所述第一未掺杂的AlGaN层之间的异质结界面处形成沟道。

公开(公告)号：US20080179694A1

公开(公告)日：2008-07-31

申请号：US12023461

申请日：2008-01-31

Applicant: Kazushi NAKAZAWA ,  Satoshi NAKAZAWA ,  Tetsuzo UEDA ,  Tsuyoshi TANAKA ,  Masahiro HIKITA

Inventor： Kazushi NAKAZAWA ,  Satoshi NAKAZAWA ,  Tetsuzo UEDA ,  Tsuyoshi TANAKA ,  Masahiro HIKITA

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66462

Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.

Abstract translation: 在FET中，第二氮化物半导体层设置在第一氮化物半导体层上，并且源电极和漏电极分别设置成使其至少一部分与第二氮化物半导体层接触。 在第二氮化物半导体层的上表面上形成凹部，位于源电极和漏电极之间。 在所述凹部上设置有栅电极以覆盖所述凹部的开口。

公开(公告)号：US20110024797A1

公开(公告)日：2011-02-03

申请号：US12903505

申请日：2010-10-13

Applicant: Kazushi NAKAZAWA ,  Satoshi NAKAZAWA ,  Tetsuzo UEDA ,  Tsuyoshi TANAKA ,  Masahiro HIKITA

Inventor： Kazushi NAKAZAWA ,  Satoshi NAKAZAWA ,  Tetsuzo UEDA ,  Tsuyoshi TANAKA ,  Masahiro HIKITA

IPC: H01L29/778 ,  H01L29/772

CPC classification number: H01L29/7787 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66462

Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.

Abstract translation: 在FET中，第二氮化物半导体层设置在第一氮化物半导体层上，并且源电极和漏电极分别设置成使其至少一部分与第二氮化物半导体层接触。 在第二氮化物半导体层的上表面上形成凹部，位于源电极和漏电极之间。 在所述凹部上设置有栅电极以覆盖所述凹部的开口。

公开(公告)号：US20090078943A1

公开(公告)日：2009-03-26

申请号：US12233011

申请日：2008-09-18

Applicant: Hidetoshi ISHIDA ,  Tetsuzo UEDA ,  Daisuke UEDA

Inventor： Hidetoshi ISHIDA ,  Tetsuzo UEDA ,  Daisuke UEDA

IPC: H01L29/15 ,  H01L21/00

CPC classification number: H01L21/84 ,  H01L27/12 ,  H01L29/2003 ,  H01L29/78681

Abstract: A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface of the diamond layer, thinning the SOI substrate, epitaxially growing an GaN layer on the thinned SOI substrate, removing the silicon substrate, and bonding, on a rear-surface of the diamond layer, a material having a thermal conductivity greater than a thermal conductivity of the silicon substrate. The SOI substrate has an outermost surface layer and a silicon oxide layer. In the thinning, the SOI substrate is thinned by selectively removed through the silicon oxide layer, so that only the outermost surface layer is left.

Abstract translation: 提供了主要由具有优异散热特性和高结晶度的氮化物半导体材料制成的氮化物半导体器件及其制造方法。 制造氮化物半导体的方法包括在硅衬底上气相沉积金刚石层，将SOI衬底粘合在金刚石层的表面上，使SOI衬底变薄，在薄化SOI衬底上外延生长GaN层，除去硅 衬底和接合在金刚石层的后表面上，具有大于硅衬底的热导率的导热率的材料。 SOI衬底具有最外表面层和氧化硅层。 在薄化中，SOI衬底通过选择性地通过氧化硅层去除而变薄，使得仅留下最外表面层。

公开(公告)号：US20110227132A1

公开(公告)日：2011-09-22

申请号：US13118945

申请日：2011-05-31

Applicant: Yoshiharu ANDA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

Inventor： Yoshiharu ANDA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

IPC: H01L29/205

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/7787

Abstract: The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract translation: 本发明的目的是提供一种具有低导通电阻的FET。 根据本发明的FET包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更高的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上的第三氮化物半导体层; 形成在所述第三氮化物半导体层上并且具有比所述第三氮化物半导体层更高的带隙能量的第四氮化物半导体层。 在第一氮化物半导体层和第二氮化物半导体层之间的异质结界面形成沟道。

公开(公告)号：US20090261362A1

公开(公告)日：2009-10-22

申请号：US12496271

申请日：2009-07-01

Applicant: Tetsuzo UEDA ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami ,  Jun Suda ,  Norio Onojima

Inventor： Tetsuzo UEDA ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami ,  Jun Suda ,  Norio Onojima

IPC: H01L33/00

CPC classification number: H01L21/02082 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/18 ,  H01L33/32

Abstract: 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectronic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes (LEDs) using conductive 4H—AlGaN interlayer on conductive 4H—SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors. The details of the epitaxial growth s and the processing procedures for the non-polar III-V nitride devices on the non-polar SiC substrates are also disclosed.

Abstract translation: 在（11-20）a面4H-SiC衬底上的4H-AlN或4H-AlGaN上形成4H-InGaAlN合金基非极性面上的光电子和电子器件。 通常，非极性4H-AlN通过分子束外延（MBE）在4H-SiC（11-20）上生长。 随后，通过用于所有层的4H-多型金属有机化学气相沉积（MOCVD）生长III-V族氮化物器件层。 由于自发和压电极化，非极性器件不包含任何内置的电场。 由于电子和空穴在量子阱中没有空间分离，非极性面上的光电器件表现出较短的发射波长的发射效率。 在导电4H-SiC衬底上使用导电4H-AlGaN夹层的激光器和发光二极管（LED）的垂直器件配置使芯片尺寸和串联电阻更小。 这种电场的消除也提高了高速和高功率晶体管的性能。 还公开了非极性SiC衬底上的非极性III-V族氮化物器件的外延生长细节和处理步骤。