公开(公告)号：US20220247055A1

公开(公告)日：2022-08-04

申请号：US17727258

申请日：2022-04-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuantao Zhou ,  Ming Wu ,  Pengyu Zhang

IPC: H01P1/185 ,  H01P11/00 ,  H01Q3/36

Abstract: This application provides a semiconductor switch device, a manufacturing method thereof, and a solid-state phase shifter. The semiconductor switch device includes a first semiconductor layer, intrinsic layers, and second semiconductor layers that are stacked. There are at least two intrinsic layers. The second semiconductors are in a one-to-one correspondence with the intrinsic layers, and each second semiconductor layer is stacked on a side of a corresponding intrinsic layer away from the first semiconductor layer. The first semiconductor layer forms one PIN diode together with each first intrinsic layer and each second semiconductor layer. Any two adjacent PIN diodes are electrically isolated. Automatic parameter matching between the two PIN diodes is implemented by using a geometrically symmetric figure with centers of the two PIN diodes aligned, to improve linearity. In addition, the entire semiconductor switch device has a compact structure, to improve an integration degree and reduce costs.

公开(公告)号：US11949024B2

公开(公告)日：2024-04-02

申请号：US17215716

申请日：2021-03-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yufeng Wang ,  Yuantao Zhou ,  Wei Wan ,  Jiang Qin

IPC: H01L29/868 ,  H01L29/06 ,  H01Q3/36 ,  H03H11/16

CPC classification number: H01L29/868 ,  H01L29/0684 ,  H01Q3/36 ,  H03H11/16

Abstract: This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.