公开(公告)号：US20180302220A1

公开(公告)日：2018-10-18

申请号：US16015072

申请日：2018-06-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yufeng Wang ,  Jing Xu

IPC: H04L9/30 ,  H04L9/08 ,  H04L9/06 ,  H04L9/32

Abstract: A user attribute matching method and a terminal are provided. The method may include generating, by a first terminal, a key by using an ElGamal algorithm, and encrypting a first user attribute value vector of the first terminal by using the public key, to form a first ciphertext. The method may also include sending the first ciphertext and the public key to a second terminal, receiving a second ciphertext and a third ciphertext that are sent by the second terminal, and decrypting the received second ciphertext and third ciphertext based on the private key. The method may also include obtaining a matching similarity between user attributes of the first terminal and the second terminal based on the decrypted second ciphertext and third ciphertext. In the method matching, efficiency is improved, and operation load of a terminal is relieved.

公开(公告)号：US11949024B2

公开(公告)日：2024-04-02

申请号：US17215716

申请日：2021-03-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yufeng Wang ,  Yuantao Zhou ,  Wei Wan ,  Jiang Qin

IPC: H01L29/868 ,  H01L29/06 ,  H01Q3/36 ,  H03H11/16

CPC classification number: H01L29/868 ,  H01L29/0684 ,  H01Q3/36 ,  H03H11/16

Abstract: This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.