公开(公告)号：US20150318592A1

公开(公告)日：2015-11-05

申请号：US14700612

申请日：2015-04-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yanzhao Zhou ,  Jian Gu ,  Wei Wan

IPC: H01P1/20 ,  C23C14/18 ,  H01P1/201 ,  C23C14/34

CPC classification number: H01P1/2002 ,  C23C14/18 ,  C23C14/185 ,  C23C14/34 ,  H01P1/201 ,  H01P11/007

Abstract: A transverse electromagnetic (TEM) mode dielectric filter and a manufacturing method thereof are provided. The mode dielectric filter provided by the present invention includes a dielectric body and a silver plating layer, where the silver plating layer covers a surface of the dielectric body, and a dielectric constant of the dielectric body is less than or equal to 21. The TEM dielectric filter provided by the present invention has a large energy storage space in a single resonant cavity of a dielectric material, and has a high quality factor. An insertion loss of the TEM dielectric filter is low, and electrical conductivity of the silver plating layer is high.

Abstract translation: 提供横向电磁（TEM）模式介质滤波器及其制造方法。 本发明提供的模式介质滤波器包括介电体和银镀层，其中镀银层覆盖电介质体的表面，电介质体的介电常数小于或等于21. TEM 由本发明提供的介质滤波器在电介质材料的单个谐振腔中具有大的能量存储空间，并具有高品质因数。 TEM介质滤波器的插入损耗低，镀银层的导电性高。

公开(公告)号：US11949024B2

公开(公告)日：2024-04-02

申请号：US17215716

申请日：2021-03-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yufeng Wang ,  Yuantao Zhou ,  Wei Wan ,  Jiang Qin

IPC: H01L29/868 ,  H01L29/06 ,  H01Q3/36 ,  H03H11/16

CPC classification number: H01L29/868 ,  H01L29/0684 ,  H01Q3/36 ,  H03H11/16

Abstract: This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.