公开(公告)号：US11043575B2

公开(公告)日：2021-06-22

申请号：US16417544

申请日：2019-05-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiaolong Ma ,  Riqing Zhang ,  Stephane Badel

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/76

Abstract: The invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove,; and forming a source and a drain in a preset source drain area along the gate length direction.

公开(公告)号：US12073863B2

公开(公告)日：2024-08-27

申请号：US17387588

申请日：2021-07-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yue Pan ,  Yanxiang Liu ,  Stephane Badel

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

Abstract: A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.

公开(公告)号：US11664440B2

公开(公告)日：2023-05-30

申请号：US17352161

申请日：2021-06-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiaolong Ma ,  Riqing Zhang ,  Stephane Badel

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/76

CPC classification number: H01L29/66545 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66787 ,  H01L29/7613 ,  H01L29/785

Abstract: An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.

公开(公告)号：US20210358531A1

公开(公告)日：2021-11-18

申请号：US17387588

申请日：2021-07-28

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yue Pan ,  Yanxiang Liu ,  Stephane Badel

IPC: G11C11/16

Abstract: A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.