A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.