-
公开(公告)号：US08068373B1
公开(公告)日：2011-11-29
申请号：US12911181
申请日：2010-10-25
IPC分类号： G11C7/10
CPC分类号： G06F1/3275 , G06F13/28 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.
摘要翻译： 公开了一种在执行存储器访问操作时管理存储器模块的电源状态的方法。 内存模块处于省电状态，直到执行涉及模块的访问操作。 将模块置于操作模式，然后执行访问操作，然后模块返回到省电状态。 还公开并要求保护使用该方法的装置和系统。
-
公开(公告)号：US07821864B2
公开(公告)日：2010-10-26
申请号：US11691321
申请日：2007-03-26
IPC分类号： G11C5/14
摘要： A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.
摘要翻译： 公开了一种在执行存储器访问操作时管理存储器模块的电源状态的方法。 内存模块处于省电状态，直到执行涉及模块的访问操作。 将模块置于操作模式，然后执行访问操作，然后模块返回到省电状态。 还公开并要求保护使用该方法的装置和系统。
-
公开(公告)号：US07218566B1
公开(公告)日：2007-05-15
申请号：US11118505
申请日：2005-04-28
IPC分类号： G11C7/00
摘要： A method of managing power states of memory modules while performing memory access operations is discussed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state.
摘要翻译： 讨论了在执行存储器访问操作时管理存储器模块的电源状态的方法。 内存模块处于省电状态，直到执行涉及模块的访问操作。 将模块置于操作模式，然后执行访问操作，然后模块返回到省电状态。
-
公开(公告)号：US07380158B2
公开(公告)日：2008-05-27
申请号：US11208165
申请日：2005-08-19
申请人： George Totolos, Jr.
发明人： George Totolos, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F11/1441 , G06F11/2015
摘要： A file server for serving data of a client from a network. The server includes disk means for storing the data. The server includes means for receiving the data from the network and sending an acknowledgment that the data has been stored to the client through the network but before the data has been stored in the disk means, the receiving means in communication with the disk means. The server includes a memory for storing the data until the data is stored in the disk means, the receiving means is in communication with the memory. The server includes a first power source for provide electricity to the disk means, the memory and the receiving means, the first power source in electrical communication with the disk means, the memory and the receiving means. The server includes a second power source that provides electricity to the memory when the first power source fails, the second power source in communication with the memory. A method for serving data of a client from a network.
摘要翻译： 用于从网络提供客户端的数据的文件服务器。 服务器包括用于存储数据的磁盘装置。 服务器包括用于从网络接收数据并通过网络向数据已经存储到数据的确认，但是在数据已经被存储在盘装置中之前，与盘装置通信的接收装置。 服务器包括用于存储数据的存储器，直到数据被存储在盘装置中，接收装置与存储器通信。 服务器包括用于向盘装置，存储器和接收装置提供电力的第一电源，与盘装置，存储器和接收装置电通信的第一电源。 服务器包括第二电源，当第一电源发生故障时向存储器供电，第二电源与存储器通信。 一种用于从网络服务客户端的数据的方法。
-
5.发明授权
公开(公告)号：US6026090A
公开(公告)日：2000-02-15
申请号：US970636
申请日：1997-11-14
CPC分类号： H04Q11/0478 , H04L2012/5662
摘要： An ATM communications system. The system includes an ATM network on which ATM cells of ATM packets travel. The system includes a host having a host memory mechanism preferably having cache lines which stores the cells. The system includes an interface having a receive memory mechanism which stores a partial packet comprising a plurality of cells received from the ATM network. The receive memory mechanism aligns with the host memory mechanism so every transfer from the receive memory mechanism of the plurality of cells to the host memory mechanism fills the host memory mechanism along cache lines of the host memory mechanism. The interface has a bus which connects to the host on which communication between the host and the interface occurs. The interface is connected to the ATM network. A method for sending ATM cells over an ATM network. An interface for a host to receive ATM cells from an ATM communication network.
摘要翻译： 一个ATM通信系统。 该系统包括ATM信元ATM信元行进的ATM网络。 该系统包括具有主机存储机构的主机，优选地具有存储单元的高速缓存行。 该系统包括具有接收存储器机制的接口，其存储包括从ATM网络接收的多个小区的部分分组。 接收存储器机构与主机存储器机制对准，因此从多个单元的接收存储器机构到主机存储器机制的每次传送都沿着主机存储器机构的高速缓存行填充主机存储器机制。 该接口具有连接到主机与接口之间发生通信的主机的总线。 该接口连接到ATM网络。 一种通过ATM网络发送ATM信元的方法。 用于主机从ATM通信网络接收ATM信元的接口。
-
公开(公告)号：US5787486A
公开(公告)日：1998-07-28
申请号：US572987
申请日：1995-12-15
CPC分类号： G06F9/52 , G06F12/0888
摘要： An apparatus and method are provided for maintaining lock characteristics while providing selective access to a cache during lock cycles. To guarantee that only one master accesses memory at a time, locked cycles are always passed to the internal arbitration unit of the memory controller, even if they are cache hits. If the local bus is not granted or cannot be guaranteed that it will be granted the bus for the locked cycle, the cycle is cancelled.
摘要翻译： 提供了一种用于在锁定周期期间保持锁定特性同时提供对高速缓存的选择性访问的装置和方法。 为了保证只有一个主机一次访问存储器，即使是高速缓存命中，锁存周期也总是传递给存储器控制器的内部仲裁单元。 如果本地总线未被授予或不能保证将被授予该锁定周期的总线，该周期将被取消。
-
7.发明授权Apparatus and implementation of a battery in a non volatile memory subsystem 失效在非易失性存储器子系统中的电池的装置和实现公开(公告)号：US07710075B1
公开(公告)日：2010-05-04
申请号：US11701103
申请日：2007-01-31
IPC分类号： H02J7/00
CPC分类号： H02J7/0068 , G06F11/3428
摘要： The battery apparatus introduced here provides a tool for reliably measuring the run time to empty of a battery used in a network storage server for protection of data during a failure mode. The battery run time to empty can be determined by a management controller based on battery information generated by a controller and received at the management controller. The information received at the management controller includes run time to empty, voltage, current and current battery capacity.
摘要翻译： 这里介绍的电池装置提供了用于可靠地测量在网络存储服务器中使用的电池的运行时间以便在故障模式期间保护数据的工具。 电池运行时间为空可以由管理控制器根据由控制器生成并在管理控制器处接收的电池信息来确定。 管理控制器收到的信息包括运行时间为空，电压，电流和当前电池容量。
-
公开(公告)号：US06216182B1
公开(公告)日：2001-04-10
申请号：US09126975
申请日：1998-07-30
IPC分类号： G06F500
CPC分类号： G06F13/385 , G06F13/24
摘要： A system for storing data. The system includes a host for processing the data. The system includes a buffer mechanism for storing data and producing interrupt signals to the host for informing the host there is data in the buffer mechanism for the host to process. The buffer mechanism adapting the production of interrupts based on the speed the host can process data. The host is in contact with the buffer mechanism. A method for serving data. The method includes the steps of storing data in a buffer mechanism. Then there is the step of sending an initial interrupt signal to a host from the buffer mechanism informing the host there is data in the buffer mechanism for the host to process. Next there is the step of transferring data in the buffer mechanism to the host. Then there is the step of processing data from the buffer mechanism with the host. Next there is the step of adapting when a subsequent interrupt signal is sent to the host based on the speed the host can process data. Then there is the step of sending the subsequent interrupt signal to the host from the buffer mechanism when there is data in the buffer mechanism for the host to process.
摘要翻译： 一种用于存储数据的系统。 该系统包括用于处理数据的主机。 该系统包括用于存储数据并产生中断信号给主机的缓冲机制，用于通知主机存在用于主机处理的缓冲机制中的数据。 缓冲机制根据主机处理数据的速度调整中断产生。 主机与缓冲机制接触。 一种服务数据的方法。 该方法包括将数据存储在缓冲机制中的步骤。 然后有一个从缓冲机制向主机发送初始中断信号的步骤，通知主机有缓冲机制中的数据供主机处理。 接下来，将缓冲机制中的数据传送到主机。 然后是与主机从缓冲机制处理数据的步骤。 接下来，基于主机可以处理数据的速度，将后续中断信号发送到主机的步骤是适应。 然后在主机处理缓冲机制中存在数据时，会从缓冲机制发送后续中断信号给主机。
-
公开(公告)号：US5613087A
公开(公告)日：1997-03-18
申请号：US392644
申请日：1995-02-23
申请人： Henry Chin , George Totolos, Jr.
发明人： Henry Chin , George Totolos, Jr.
CPC分类号： G11C29/24 , G11C29/46 , G06F12/0802
摘要： The cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows reading and writing directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L.sub.1) and second level (L.sub.2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuits in the L.sub.2 cache ignore the command on the EADS# command line. However, the tag RAM test circuitry in the L.sub.2 cache recognizes the extended EADS# strobe providing a path to access all bit locations in a tag RAM for both read and write cycles to test the tag RAM or to load those bit positions to selected states in testing other portions of the cache.
摘要翻译： 基于Intel Pentium处理器的计算机系统中的二级缓存的高速缓存控制器包含允许直接读取和写入所有标签RAM数据位置的测试电路。 该电路响应修改的外部地址选通（EADS＃）命令来调用标签测试周期。 EADS＃命令通常用于系统的SNOOP读取周期。 在SNOOP周期中，主存储器控制器调用EADS＃命令以对存储在那些高速缓存中的修改信息请求第一级（L1）和第二级（L2）高速缓存。 在标签测试周期中，EADS＃命令行的持续时间为正常SNOOP读周期的两倍。 由于其增加的长度，L2缓存中的SNOOP周期电路忽略EADS＃命令行上的命令。 然而，L2缓存中的标签RAM测试电路识别扩展的EADS＃选通提供访问标签RAM中读取和写入周期的所有位位置的路径，以测试标签RAM或将这些位位置加载到选定的状态 测试缓存的其他部分。
-
10.发明授权公开(公告)号：US08086914B2
公开(公告)日：2011-12-27
申请号：US13087710
申请日：2011-04-15
IPC分类号： G11C29/00
CPC分类号： G06F12/0246 , G06F11/1666 , G06F11/20 , G06F2212/1032 , G06F2212/7208 , G11C29/76
摘要： Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.017 秒)
