Abstract:
Programmable controllers are connected in a ring by serial data links. Each controller periodically transmits information packets on the ring which contain its I/O image table data. All controllers on the ring receive such data and store it in their data tables, and such data is thus available for examination by each controller processor during its execution of the user's control program.
Abstract:
A programmable controller includes a microprocessor which operates in response to machine instructions stored in a read-only memory. A control program comprised of programmable controller-type instructions is stored in a random access memory. These are executed by translating their operation codes into the starting addresses of corresponding sets of machine instructions. In addition, one or more "universal instructions" may be contained in the control program, and when these are read from the random-access memory, they are translated to enable the microprocessor to execute a user defined set of microprocessor machine instructions. These user defined machine instructions may be stored in a read-only memory or they may be stored in the random access memory with the control program. The programmable controller may thus effectively be programmed in two languages, a programmable controller language and a microprocessor machine language.
Abstract:
A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.
Abstract:
An industrial automation controller module includes a main module and an energy storage module (ESM) releasably connected to the main module. The ESM includes a back-up electrical power source such as a battery or a capacitor that is electrically connected to processor circuitry of the main module when the ESM is physically connected to the main module. In case of interruption of operating power to the processor circuitry of the main module, the back-up power source of the ESM supplies back-up power to the main module to allow for completion of an emergency save operation to save data to non-volatile memory in the main module. If the ESM includes a capacitor back-up power source, it is charged by the main module and the capacitor charge is dissipated if the ESM is separated from the main module. In all cases, the ESM can include one or more configuration parameters stored therein that allow the main module to validate (or not) the ESM for the requirements of the main module, with respect to type of back-up power source, product code or model, capacity of back-up power source, and the like. The main module can also initiate periodic testing of the back-up power source of the ESM.
Abstract:
A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.
Abstract:
A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.
Abstract:
An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.
Abstract:
A multi-tasking industrial controller for real-time control of machinery and the like permits the use of both periodic and event driven tasks by establishing a hierarchy of both task types in the form of priorities that resolve conflicts between events of the same and different types. Each task may access a common "global" memory area to communicate information and timing with other tasks and so as to coordinate the overall industrial control process. Trouble-shooting of the task software is made possible by a hardware address monitor which may be programmed to identify access of a particular memory location or range by any task and to record information about the particular task causing that global memory access.
Abstract:
A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.
Abstract:
An electronic module and chassis/module installation and cooling method are disclosed. The installation comprises a chassis including a metallic heat input region. An electronic module including an electronic component is adapted to be connected to the chassis. An uninterrupted thermal pathway thermally connects the electronic component of the module to the heat input region of the chassis. The thermal pathway comprises a chimney, a heat channel thermally connected to the chimney, and a heat output block thermally connected to the heat channel. A first electrically insulative non-metallic layer thermally couples the chimney to the electronic component. A second electrically insulative non-metallic layer thermally couples the heat output block to the chassis heat input region.