公开(公告)号：US09214541B2

公开(公告)日：2015-12-15

申请号：US13780912

申请日：2013-02-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravikumar Ramachandran ,  Ying Li ,  Richard S. Wise

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

Abstract translation: 替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。 介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷 平坦化介电层。 电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。