公开(公告)号：US10741439B2

公开(公告)日：2020-08-11

申请号：US16411775

申请日：2019-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Martin J. O'Toole ,  Terry A. Spooner ,  Jason E. Stephens

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033 ,  H01L23/532 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

公开(公告)号：US10566231B2

公开(公告)日：2020-02-18

申请号：US15966032

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin J. O'Toole ,  Christopher J. Penny ,  Jae O. Choo ,  Adam L. da Silva ,  Craig Child ,  Terry A. Spooner ,  Hsueh-Chung Chen ,  Brendan O'Brien ,  Keith P. Donegan

IPC: H01L21/768 ,  H01L23/532

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

公开(公告)号：US20190333805A1

公开(公告)日：2019-10-31

申请号：US15966032

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin J. O'Toole ,  Christopher J. Penny ,  Jae O. Choo ,  Adam L. da Silva ,  Craig Child ,  Terry A. Spooner ,  Hsueh-Chung Chen ,  Brendan O'Brien ,  Keith P. Donegan

IPC: H01L21/768

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

公开(公告)号：US10340180B1

公开(公告)日：2019-07-02

申请号：US15872314

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Martin J. O'Toole ,  Terry A. Spooner ,  Jason E. Stephens

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/033 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53271

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.