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    SADP method with mandrel undercut spacer portion for mandrel space dimension control
    3.
    发明授权
    SADP method with mandrel undercut spacer portion for mandrel space dimension control 有权

    公开(公告)号：US10395941B1

    公开(公告)日：2019-08-27

    申请号：US16106174

    申请日：2018-08-21

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ravi P. Srivastava ,  Hsueh-Chung Chen

    IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/8234

    摘要： A self-aligned double patterning (SADP) method is disclosed. The method may include forming a mandrel over an underlying layer, and undercutting the mandrel forming an undercut space under opposing sides of the mandrel. A pair of spacers may be formed adjacent the mandrel, each spacer including a vertical spacer portion on each side of the mandrel and an undercut spacer portion extending into the undercut space from the vertical spacer portion, the undercut spacer portions defining a sub-lithographic lateral dimension therebetween. The mandrels may be removed and, a sub-lithographic feature etched into at least the underlying layer using the spacers.

    DOUBLE SELF ALIGNED VIA PATTERNING
    4.
    发明申请
    DOUBLE SELF ALIGNED VIA PATTERNING 有权
    双向自对准通过方式

    公开(公告)号：US20140363969A1

    公开(公告)日：2014-12-11

    申请号：US13913823

    申请日：2013-06-10

    申请人： Globalfoundries Inc. ,  International Business Machines Corporation

    发明人： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

    摘要： A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

    摘要翻译： 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔打开通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

    Making an efuse
    5.
    发明授权
    Making an efuse 有权

    公开(公告)号：US09646929B2

    公开(公告)日：2017-05-09

    申请号：US13916669

    申请日：2013-06-13

    申请人： GLOBALFOUNDRIES INC.

    发明人： Hsueh-Chung Chen ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Ailian Zhao

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5256 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

    MAKING AN EFUSE
    6.
    发明申请
    MAKING AN EFUSE 有权
    做一个EFUSE

    公开(公告)号：US20140367826A1

    公开(公告)日：2014-12-18

    申请号：US13916669

    申请日：2013-06-13

    申请人： GLOBALFOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Hsueh-Chung Chen ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Ailian Zhao

    IPC分类号： H01L21/768 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

    摘要翻译： 公开了晶片芯片和芯片的设计方法。 形成具有第一临界尺寸的第一熔丝，并且在芯片的层中形成具有第二临界尺寸的第二熔丝。 可以施加电压以烧尽第一保险丝和第二保险丝中的至少一个。 第一保险丝的第一关键尺寸可以是将第一掩模施加到该层并且将具有第一特性的光施加到掩模。 第二保险丝的第二关键尺寸可以是将第二掩模应用于该层并且将具有第二特性的光施加到掩模。

    MULTIPLE PATTERNING WITH LITHOGRAPHICALLY-DEFINED CUTS
    7.
    发明申请
    MULTIPLE PATTERNING WITH LITHOGRAPHICALLY-DEFINED CUTS 审中-公开

    公开(公告)号：US20200111677A1

    公开(公告)日：2020-04-09

    申请号：US16154306

    申请日：2018-10-08

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ravi Prakash Srivastava ,  Hsueh-Chung Chen ,  Steven McDermott ,  Martin O'Toole ,  Brendan O'Brien ,  Terry A. Spooner

    IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768

    摘要： Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.

    Double self aligned via patterning
    10.
    发明授权
    Double self aligned via patterning 有权
    双重自对准通过图案化

    公开(公告)号：US09219007B2

    公开(公告)日：2015-12-22

    申请号：US13913823

    申请日：2013-06-10

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

    发明人： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

    IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311

    CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

    摘要： A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

    摘要翻译： 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。