公开(公告)号：US20240427499A1

公开(公告)日：2024-12-26

申请号：US18650171

申请日：2024-04-30

Applicant: Fujitsu Limited

Inventor： Ichiro YOKOKURA ,  Junichi SUGIYAMA ,  Yusuke TANABE

IPC: G06F3/06

Abstract: A transmission device transmits signals between a server and an opposing device. The transmission device includes a memory and includes a controller that controls a first queue and a second queue in the server and controls the memory. When detecting issuance of a processing request from the server to the opposing device, the controller queues the processing request in the first queue, obtains the data from the server according to the processing request, and stores the obtained data in the memory. After requesting the transfer of the data and the processing request to the opposing device, before executing the processing request in the opposing device, the controller queues the processing completion of the processing in the second queue and releases the queue of the processing completion.

公开(公告)号：US20230379078A1

公开(公告)日：2023-11-23

申请号：US18159105

申请日：2023-01-25

Applicant: Fujitsu Limited

Inventor： Yusuke TANABE ,  Nobuyuki AKIZAWA

IPC: H04L1/00 ,  H04B10/516

CPC classification number: H04L1/0041 ,  H04B10/516

Abstract: An optical transmission apparatus includes: a first processing circuit that performs, on a forward error correction (FEC) frame obtained by adding FEC to a frame that directly accommodates a client signal, error correction based on the FEC, and acquires an amount of errors for which correction failed in the error correction as an uncorrectable amount; and a second processing circuit that estimates the number of bit errors of the errors based on the uncorrectable amount, and outputs information that includes the estimated number of bit errors.

公开(公告)号：US20250156363A1

公开(公告)日：2025-05-15

申请号：US18913275

申请日：2024-10-11

Applicant: Fujitsu Limited

Inventor： Ichiro YOKOKURA ,  Junichi SUGIYAMA ,  Yusuke TANABE

IPC: G06F13/42 ,  G06F3/06 ,  H04L67/1097

Abstract: A memory drive device includes a memory, and a processor coupled to the memory and configured to when receiving a specific packet according to a connection standard specified in Computer eXpress Link (CXL), store data included as a part of the specific packet in a buffer and determine whether addresses included as the part of the specific packet together with the data are consecutive, when the addresses are consecutive, generate first information in which information of the addresses that are consecutive and information of the data associated with the addresses that are consecutive are aggregated, and notify a memory device of a write request of the data to the memory device, based on the first information and the communication standard when the data stored in the buffer is written to the memory device specified by a communication standard that does not support the CXL.