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    Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength
    2.
    发明授权
    Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength 有权
    具有动态可变p沟道金属氧化物半导体（PMOS）强度的六晶体管（6T）静态随机存取存储器（SRAM）

    公开(公告)号：US07177176B2

    公开(公告)日：2007-02-13

    申请号：US10883609

    申请日：2004-06-30

    Applicant: Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih (Eric) Wang

    Inventor： Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih (Eric) Wang

    IPC: G11C11/00 ,  G11C5/14 ,  G11C7/10

    CPC classification number: G11C11/417 ,  G11C11/412

    Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

    Abstract translation: 在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。 单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。 在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。 在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

    Dynamic multi-Vcc scheme for SRAM cell stability control
    3.
    发明授权
    Dynamic multi-Vcc scheme for SRAM cell stability control 有权

    公开(公告)号：US07079426B2

    公开(公告)日：2006-07-18

    申请号：US10950740

    申请日：2004-09-27

    Applicant: Kevin Zhang ,  Fatih Hamzaoglu ,  Lin Ma

    Inventor： Kevin Zhang ,  Fatih Hamzaoglu ,  Lin Ma

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C5/14 ,  G11C11/413

    Abstract: A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

    Bitline floating during non-access mode for memory arrays
    4.
    发明授权
    Bitline floating during non-access mode for memory arrays 有权
    位线在内存阵列的非访问模式下浮动

    公开(公告)号：US08982659B2

    公开(公告)日：2015-03-17

    申请号：US12645623

    申请日：2009-12-23

    Applicant: Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    Inventor： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    IPC: G11C5/14 ,  G11C7/12 ,  G11C11/413

    CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C11/413

    Abstract: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    Abstract translation: 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

    Cache leakage shut-off mechanism
    6.
    发明申请
    Cache leakage shut-off mechanism 有权
    缓存泄漏关闭机制

    公开(公告)号：US20070005999A1

    公开(公告)日：2007-01-04

    申请号：US11174204

    申请日：2005-06-30

    Applicant: Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

    Inventor： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

    IPC: G06F1/00

    CPC classification number: G06F1/32 ,  G06F1/3287 ,  G11C11/417 ,  Y02D10/171

    Abstract: In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

    Abstract translation: 在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。 本文公开了其它实施例。 睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。 高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。 有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。

    Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength
    7.
    发明申请
    Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength 有权
    具有动态可变p沟道金属氧化物半导体（PMOS）强度的六晶体管（6T）静态随机存取存储器（SRAM）

    公开(公告)号：US20060002177A1

    公开(公告)日：2006-01-05

    申请号：US10883609

    申请日：2004-06-30

    Applicant: Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih Wang

    Inventor： Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih Wang

    IPC: G11C11/00

    CPC classification number: G11C11/417 ,  G11C11/412

    Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

    Abstract translation: 在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。 单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。 在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。 在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

    BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS
    9.
    发明申请
    BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS 有权
    用于存储阵列的非访问模式下的位线浮动

    公开(公告)号：US20110149666A1

    公开(公告)日：2011-06-23

    申请号：US12645623

    申请日：2009-12-23

    Applicant: Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

    Inventor： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

    IPC: G11C7/00 ,  G11C5/14

    CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C11/413

    Abstract: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    Abstract translation: 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

    Dynamic body bias with bias boost
    10.
    发明申请
    Dynamic body bias with bias boost 审中-公开
    具有偏压增强的动态身体偏倚

    公开(公告)号：US20070153610A1

    公开(公告)日：2007-07-05

    申请号：US11323361

    申请日：2005-12-29

    Applicant: Fatih Hamzaoglu ,  Kevin Zhang ,  Yih Wang

    Inventor： Fatih Hamzaoglu ,  Kevin Zhang ,  Yih Wang

    IPC: G11C5/14

    CPC classification number: G11C5/146 ,  H03K19/0016

    Abstract: For one disclosed embodiment, circuitry may bias one or more wells of a substrate from a first state to a second state. Bias by the circuitry of one or more wells of the substrate to the second state may be boosted. Other embodiments are also disclosed.

    Abstract translation: 对于一个所公开的实施例，电路可以将衬底的一个或多个阱从第一状态偏置到第二状态。 通过衬底的一个或多个孔的电路到第二状态的偏置可以被提升。 还公开了其他实施例。

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