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公开(公告)号:US20210234031A1
公开(公告)日:2021-07-29
申请号:US17129552
申请日:2020-12-21
申请人: FUJITSU LIMITED
发明人: Kozo MAKIYAMA , Shirou OZAKI , Atsushi YAMADA , Junji KOTANI
IPC分类号: H01L29/778
摘要: A disclosed semiconductor device includes an electron transit layer; an electron supply layer disposed above the electron transit layer; a source electrode, a drain electrode, and a gate electrode, the source electrode, the drain electrode, and the gate electrode being disposed on the electron supply layer; a first capping layer disposed on the electron supply layer between the gate electrode and the drain electrode; and a negative charge generation layer disposed on the first capping layer, the negative charge generation layer being configured to generate a negative charge.
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公开(公告)号:US20140091313A1
公开(公告)日:2014-04-03
申请号:US13935821
申请日:2013-07-05
申请人: FUJITSU LIMITED
IPC分类号: H01L29/205
CPC分类号: H01L29/205 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02581 , H01L21/0262 , H01L29/1066 , H01L29/2003 , H01L29/201 , H01L29/207 , H01L29/36 , H01L29/42316 , H01L29/517 , H01L29/66462 , H01L29/7786
摘要: A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer.
摘要翻译: 一种半导体装置,包括:基板; 形成在所述基板上的缓冲层; 形成在缓冲层上的第一半导体层; 以及形成在所述第一半导体层上的第二半导体层。 此外,缓冲层由AlGaN形成并掺杂Fe,缓冲层包括彼此不同的Al成分比的多个层,第一层的Al成分比大于第二层的Al成分比 所述第一层的Fe浓度小于所述第二层的Fe浓度,所述第一层和所述第二层包含在所述多层中,所述第一层形成在所述第二层的基板侧。
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公开(公告)号:US20240297246A1
公开(公告)日:2024-09-05
申请号:US18648169
申请日:2024-04-26
申请人: FUJITSU LIMITED
发明人: Shirou OZAKI , Junji KOTANI , Atsushi YAMADA
IPC分类号: H01L29/778 , H01L21/02 , H01L29/20 , H01L29/205 , H01L29/66
CPC分类号: H01L29/7786 , H01L21/02389 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L29/2003 , H01L29/205 , H01L29/66462
摘要: A semiconductor device includes an AlN substrate, a semiconductor laminated structure, disposed above the substrate, and including an electron transit layer and an electron supply layer made of a nitride semiconductor, respectively, and a gate electrode, a source electrode, and a drain electrode disposed above the electron supply layer. The electron transit layer is located at a lowermost position of the semiconductor laminated structure. The gate electrode has a gate length of 0.3 μm or less, and a ratio of a thickness of the semiconductor laminated structure with respect to the gate length of the gate electrode is 4.0 or less.
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公开(公告)号:US20220013642A1
公开(公告)日:2022-01-13
申请号:US17209869
申请日:2021-03-23
申请人: FUJITSU LIMITED
发明人: Junya YAITA , Junji KOTANI , Atsushi YAMADA , Kozo MAKIYAMA
IPC分类号: H01L29/20 , H01L29/205 , H01L29/78 , H01L29/10
摘要: A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.
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公开(公告)号:US20220069112A1
公开(公告)日:2022-03-03
申请号:US17228002
申请日:2021-04-12
申请人: FUJITSU LIMITED
发明人: Shirou OZAKI , Junji KOTANI , Atsushi YAMADA
IPC分类号: H01L29/778 , H01L29/20 , H01L29/205 , H01L21/02 , H01L29/66
摘要: A semiconductor device includes an AlN substrate, a semiconductor laminated structure, disposed above the substrate, and including an electron transit layer and an electron supply layer made of a nitride semiconductor, respectively, and a gate electrode, a source electrode, and a drain electrode disposed above the electron supply layer. The electron transit layer is located at a lowermost position of the semiconductor laminated structure. The gate electrode has a gate length of 0.3 μm or less, and a ratio of a thickness of the semiconductor laminated structure with respect to the gate length of the gate electrode is 4.0 or less.
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公开(公告)号:US20180047840A1
公开(公告)日:2018-02-15
申请号:US15791878
申请日:2017-10-24
申请人: FUJITSU LIMITED
发明人: Norikazu NAKAMURA , Junji KOTANI
IPC分类号: H01L29/778 , H01L21/02 , H01L29/66 , H01L29/20 , H01L29/205
摘要: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor above a substrate, a second semiconductor layer formed of a material including InAlN or InAlGaN above the first semiconductor layer, a third semiconductor layer formed of a material including AlN above the second semiconductor layer, a fourth semiconductor layer formed of a material including GaN above the third semiconductor layer, a gate electrode formed above the fourth semiconductor layer, and a source electrode and a drain electrode formed on any one of the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.
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7.
公开(公告)号:US20230037148A1
公开(公告)日:2023-02-02
申请号:US17728389
申请日:2022-04-25
申请人: FUJITSU LIMITED
发明人: Shirou OZAKI , Junji KOTANI , Toshihiro OHKI , Naoya OKAMOTO
IPC分类号: H01L29/778 , H03F3/213 , H03F1/32 , H01L29/205 , H01L21/02 , H01L29/66
摘要: A compound semiconductor device includes a carrier supply layer, a channel layer disposed over the carrier supply layer and configured to include InGaAs, and an etching stopper layer disposed over the channel layer, and configured to include a first layer disposed over the channel layer and configured to include Inx1Ga1-x1P, and a second layer disposed over the first layer and configured to include Inx2Ga1-x2P, wherein x1 is greater than 0 and less than or equal to 1, x2 is greater than or equal to 0 and less than 1, and x1 is greater than x2.
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公开(公告)号:US20130257539A1
公开(公告)日:2013-10-03
申请号:US13732596
申请日:2013-01-02
申请人: FUJITSU LIMITED
发明人: Junji KOTANI
IPC分类号: H01L29/20
CPC分类号: H01L29/2003 , H01L29/0649 , H01L29/407 , H01L29/66462 , H01L29/7787 , H01L2224/0603 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要: A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer.
摘要翻译: 化合物半导体器件包括:衬底; 形成在所述基板上的缓冲层; 形成在缓冲层上的电子转移层和给电子层; 形成在供电层上的栅电极,源电极和漏电极; 以及嵌入电极,与该栅电极,源极电极和漏电极无关的电位被提供给该电极以控制缓冲层的电位。
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