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公开(公告)号：US12235346B2
公开(公告)日：2025-02-25
申请号：US17573177
申请日：2022-01-11
Inventor： Min Park , Bon Tae Koo , Kyung Hwan Park , Pil Jae Park , Jang Hong Choi
IPC: G01S13/536 , G01S7/35 , G01S13/58
Abstract: Disclosed is a radar device capable of operating in a dual mode, which includes a transmitter that includes a first signal generator that generates a Doppler radar signal and a second signal generator that generates a Frequency Modulated Continuous Wave (FMCW) radar signal, a receiver that receives a reflected signal reflected from a target and converts the reflected signal to a digital signal, a signal processing circuit that processes the digital signal differently depending on the dual mode to output an output signal, a signal analysis circuit that analyzes the output signal, and a controller that controls operations of the transmitter, the receiver, the signal processing circuit, and the signal analysis circuit, and the dual mode includes a first mode in which the first signal generator is activated and a second mode in which the second signal generator is activated.
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公开(公告)号：US12107555B2
公开(公告)日：2024-10-01
申请号：US17317483
申请日：2021-05-11
Inventor： Min Park , Jang Hong Choi , Bon Tae Koo , Kisu Kim , Kyung Hwan Park
CPC classification number: H03F3/245 , H03F3/2171 , H03G3/3042 , H03F2200/451
Abstract: Provided is a drive amplifier. A drive amplifier may include: a main circuit configured to receive an RF input signal and output a first RF output signal; and a selective bias adjustment circuit comprising a first common gate transistor to which a first common gate bias voltage is applied and a second common gate transistor to which a second common gate bias voltage is applied, and configured to output a second RF output signal using the first common gate transistor and the second common gate transistor.
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公开(公告)号：US09780891B2
公开(公告)日：2017-10-03
申请号：US15229950
申请日：2016-08-05
Inventor： Ik Soo Eo , Sang-Kyun Kim , Cheon Soo Kim , Jang Hong Choi
CPC classification number: H04B17/14 , H04B17/0085 , H04B17/104
Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.
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Patent Agency Ranking
公开(公告)号：US10044385B2
公开(公告)日：2018-08-07
申请号：US15074881
申请日：2016-03-18
Inventor： Dong Woo Kang , Cheon Soo Kim , Jang Hong Choi
Abstract: Provided is a transmitter. The transmitter includes a signal combiner configured to amplify a first differential radio frequency (RF) signal modulated to be transmitted through a first frequency band and a second differential RF signal modulated to be transmitted through a second frequency band non-adjacent to the first frequency band and summate the amplified first differential RF signal and the amplified second differential RF signal in a current mode to generate an RF signal and a power amplifier configured to amplify the generated RF signal.
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公开(公告)号：US20240377507A1
公开(公告)日：2024-11-14
申请号：US18656966
申请日：2024-05-07
Inventor： Seong Mo Park , Kyung Hwan Park , Pil Jae Park , Byounggun Choi , Jang Hong Choi
Abstract: Disclosed is a radar device which includes a transmission circuit that emits a first transmission signal and a second transmission signal, and a reception circuit that receives a first reception signal associated with the first transmission signal and a second reception signal associated with the second transmission signal, converts the first reception signal into first data, and converts the second reception signal into second data.
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公开(公告)号：US11799424B2
公开(公告)日：2023-10-24
申请号：US17585009
申请日：2022-01-26
Inventor： Jang Hong Choi , Bon Tae Koo , Kyung Hwan Park , Min Park , Seon-Ho Han
CPC classification number: H03D3/247 , H03D3/02 , H03D7/00 , H03F3/04 , H04L27/22 , G01S7/354 , G01S7/358 , H03K2005/00078 , H03K2005/00286
Abstract: Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.
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公开(公告)号：US11837996B2
公开(公告)日：2023-12-05
申请号：US17585009
申请日：2022-01-26
Inventor： Jang Hong Choi , Bon Tae Koo , Kyung Hwan Park , Min Park , Seon-Ho Han
CPC classification number: H03D3/247 , H03D3/02 , H03D7/00 , H03F3/04 , H04L27/22 , G01S7/354 , G01S7/358 , H03K2005/00078 , H03K2005/00286
Abstract: Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.
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公开(公告)号：US09509283B2
公开(公告)日：2016-11-29
申请号：US14120351
申请日：2014-05-14
Inventor： Mi Jeong Park , Jang Hong Choi , Ik Soo Eo
CPC classification number: H03H17/0657 , H03H2218/085
Abstract: Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.
Abstract translation: 公开了一种基于时间分配算法的内插滤波器。 内插滤波器包括使能信号产生部分产生用于内插滤波器的操作的使能信号，产生输入值的输入值产生部分，基于第一使能信号和第一输入值产生第一输出值的第一计算部分， 第二计算部分，基于第二使能信号和第二输入值产生第二输出值;以及输出值选择部分，选择所述第一输出值和所述第二输出值中的最终输出值。 因此，可以保证输出数据的连续性，并且可以通过使用时间分配算法来共享硬件，使得可以减少内插滤波器的总大小。
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