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公开(公告)号:US20170228241A1
公开(公告)日:2017-08-10
申请号:US15045057
申请日:2016-02-16
Inventor: Yong Joo KIM , Kyung Hee LEE , Chae Deok LIM
CPC classification number: G06F9/44505 , G06F9/5072 , G06F11/16 , G06F15/7867 , Y02D10/12 , Y02D10/13
Abstract: Provided herein are an acceleration system and a driving method thereof. The acceleration system includes a configuration memory, and a plurality of processing units which receive works from the configuration memory, perform the received works, and output results of the performed works. Each of the processing units include an n (n is an integer of three or more) number of processing elements which generate an n number of results, and each of which receives one of the works, and a select module which selects, using a majority-vote system, one of the n number of generated results and generates a selected result.
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公开(公告)号:US20150242308A1
公开(公告)日:2015-08-27
申请号:US14610040
申请日:2015-01-30
Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , UNIST ACADEMY-INDUSTRY RESEARCH CORPORATION
Inventor: Yong Joo KIM , Jin Yong LEE , Yun Heung PAEK , Jong Eun LEE
CPC classification number: G06F11/27 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F2212/1016 , G06F2212/1028 , G06F2212/251 , G06F2212/62 , G11C5/025 , G11C29/00 , H01L25/18 , H01L2924/0002 , Y02D10/13 , H01L2924/00
Abstract: Provided is a memory device including a logic layer including at least one of a peripheral device, an interface, and a built-in self-test (BIST) module and a reconfigurable accelerator (RA), and at least one data layer to store data, wherein the RA is positioned in a vacant space of the logic layer and processes at least a portion of a task processed by the memory device.
Abstract translation: 提供了包括包括外围设备,接口和内置自检(BIST)模块和可重新配置加速器(RA)中的至少一个)的逻辑层的存储设备,以及存储数据的至少一个数据层 ,其中所述RA位于所述逻辑层的空闲空间中,并处理由所述存储器件处理的任务的至少一部分。
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