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公开(公告)号:US20140004809A1
公开(公告)日:2014-01-02
申请号:US13792941
申请日:2013-03-11
Inventor: Jin Cheol JEONG , Dong Pil CHANG , In Bok YOM
IPC: H04B1/04
CPC classification number: H04B1/0475 , H03D7/1408 , H03D2200/009
Abstract: Provided is a frequency mixer including: an oscillator configured to output an LO signal; a first converter configured to convert an input IF signal into different first and second IF signals; a first mixer configured to output a first RF signal in which the first IF signal is mixed with the LO signal and a first leakage signal; a second mixer configured to output a second RF signal in which the second IF signal is mixed with the LO signal and a second leakage signal; and a second converter configured to mix and attenuate the first and second leakage signals and output an RF signal in which the first and second RF signals are mixed, in order to minimize leakage power of an LO signal generated in a local oscillator in a transmitter for a communication system using a high frequency of 70 GHz or higher, such as an E-band.
Abstract translation: 提供一种混频器,包括:被配置为输出LO信号的振荡器; 第一转换器,被配置为将输入IF信号转换成不同的第一和第二IF信号; 第一混频器,被配置为输出其中所述第一IF信号与所述LO信号混合的第一RF信号和第一泄漏信号; 第二混频器,被配置为输出其中所述第二IF信号与所述LO信号和第二泄漏信号混合的第二RF信号; 以及第二转换器,被配置为混合和衰减第一和第二泄漏信号并输出其中混合第一和第二RF信号的RF信号,以便最小化在发射机中的本地振荡器中产生的LO信号的泄漏功率, 使用70GHz以上的高频的通信系统,例如E波段。
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公开(公告)号:US20240429599A1
公开(公告)日:2024-12-26
申请号:US18750150
申请日:2024-06-21
Inventor: Jun Han LIM , Hong Yeol LEE , Jin Cheol JEONG , Dong Pil CHANG
Abstract: A calibration system of a phased array antenna is disclosed, including an antenna device comprising the phased array antenna, a measurement device configured to measure outputted signals from each radiating element arrayed in the phased array antenna to generate measured value data, and an analysis device configured to analyze the measured value data to generate and transmit analysis data to the antenna device, wherein the antenna device is configured to determine a phase offset to be applied to each radiating element based on the analysis data.
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公开(公告)号:US20190123778A1
公开(公告)日:2019-04-25
申请号:US15896809
申请日:2018-02-14
Inventor: Jin Cheol JEONG , Dong Hwan SHIN , Man Seok UHM , IN BOK YOM
Abstract: A monolithic microwave integrated circuit (MIMIC) for a phased array antenna system, and a phased array antenna system including the MIMIC are provided. The MIMIC includes a first amplifier including a first input terminal and a first output terminal, a second amplifier including a second input terminal and a second output terminal, a first switch connectable to the first input terminal and the second output terminal, and a second switch connectable to the first output terminal and the second input terminal.
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公开(公告)号:US20180123211A1
公开(公告)日:2018-05-03
申请号:US15584662
申请日:2017-05-02
Inventor: Dong Pil CHANG , Hongyeol LEE , Changsoo KWAK , Dong Hwan SHIN , In Bok YOM , Jin Cheol JEONG
Abstract: Disclosed is a radio frequency low-loss power divider/combiner and power amplifier including the same, the power divider/combiner including a waveguide and a converter configured to convert an input signal received from an input signal terminal into a plurality of output signals and output the plurality of output signals to a plurality of output signal terminals corresponding to the plurality of output signals through the waveguide, wherein the waveguide includes the converter.
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公开(公告)号:US20170093384A1
公开(公告)日:2017-03-30
申请号:US15214738
申请日:2016-07-20
Inventor: Dong Hwan SHIN , Seong Mo MOON , In Bok YOM , Dong Pil CHANG , Jin Cheol JEONG
IPC: H03K5/134
CPC classification number: H03K5/134 , H03K2005/00195
Abstract: Provided is an active true time delay apparatus for delaying a time and producing a gain in a superhigh frequency band using a field effect transistor (FET) and a similar semiconductor device. The active true time delay apparatus may include a delayer configured to delay an input signal for a predetermined length of time using at least one FET element connected in a distributed amplifier structure and an outputter configured to output the delayed input signal, and the delayer is disposed on a transmission line between an inputter and the outputter.
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公开(公告)号:US20150137877A1
公开(公告)日:2015-05-21
申请号:US14308931
申请日:2014-06-19
Inventor: Yun Ho CHOI , Youn Sub NOH , Hong Gu JI , Jin Cheol JEONG , In Bok YOM
IPC: G05F3/16
Abstract: Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node.
Abstract translation: 提供偏置电路。 偏置电路包括:连接在接地端子和第一节点之间的第一电阻器; 具有连接到第一节点的漏极和连接到第二节点的源极的第一偏置晶体管; 具有连接到第二节点的漏极和连接到负电压端子的源极的第二偏置晶体管; 具有连接到所述接地端子的漏极和连接到第三节点的源极的第三偏置晶体管; 以及连接在所述第三节点和所述负电压端子之间的第二电阻器,其中所述第一偏置晶体管的栅极连接到所述第二节点; 第二偏置晶体管的栅极连接到负电压端子; 第三偏置晶体管的栅极连接到第一节点; 并且通过第三节点输出栅极偏置电压信号。
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