公开(公告)号：US20050077605A1

公开(公告)日：2005-04-14

申请号：US10986104

申请日：2004-11-12

申请人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

发明人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

IPC分类号： G02F1/13 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  H01L23/02 ,  H01L23/28 ,  H01L27/14

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

摘要： A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

摘要翻译： 提供了一种用于晶片级封装的方法和结构，其利用半导体晶片或透明基板上的多个间隔壁，其具有决定密封剂位置的能力。 结果，装置的尺寸由密封剂和间隔壁的位置决定，因此，在对整个半导体晶片进行模切工艺之后，缩小感光区和密封剂之间的距离将增加总模量 。 此外，半导体工艺决定间隔壁的高度，从而由于半导体晶片和透明基板之间的间隙的均匀性和密封剂的宽度将是 受控。

公开(公告)号：US07087464B2

公开(公告)日：2006-08-08

申请号：US10986104

申请日：2004-11-12

申请人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

发明人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

IPC分类号： H01L21/44

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

摘要： A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

摘要翻译： 提供了一种用于晶片级封装的方法和结构，其利用半导体晶片或透明基板上的多个间隔壁，其具有决定密封剂位置的能力。 结果，装置的尺寸由密封剂和间隔壁的位置决定，因此，在对整个半导体晶片进行模切工艺之后，缩小感光区和密封剂之间的距离将增加总模量 。 此外，半导体工艺决定间隔壁的高度，从而由于半导体晶片和透明基板之间的间隙的均匀性和密封剂的宽度将是 受控。

公开(公告)号：US20050077603A1

公开(公告)日：2005-04-14

申请号：US10680434

申请日：2003-10-08

申请人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

发明人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

IPC分类号： G02F1/13 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  H01L23/02 ,  H01L23/28 ,  H01L27/14

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

摘要： A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

公开(公告)号：USD676747S1

公开(公告)日：2013-02-26

申请号：US29418556

申请日：2012-04-18

申请人： Yi-Ming Chang

设计人： Yi-Ming Chang

公开(公告)号：US08116101B2

公开(公告)日：2012-02-14

申请号：US12368963

申请日：2009-02-10

申请人： Yi-Ming Chang ,  Yung-Chih Kuo ,  Chung-Teng Wu

发明人： Yi-Ming Chang ,  Yung-Chih Kuo ,  Chung-Teng Wu

IPC分类号： H05K7/02

CPC分类号： G06F1/1656 ,  G06F1/1616

摘要： An electronic device including a housing, a circuit board, a first non-metal conductive cushion and a fastening element is provided. The circuit board is disposed in the housing. The first non-metal conductive cushion is disposed between the circuit board and the housing. A potential of the first non-metal conductive cushion is equal to a potential of the housing. The fastening element fastens the circuit board and the non-metal conductive cushion to the housing.

摘要翻译： 提供了一种包括壳体，电路板，第一非金属导电衬垫和紧固元件的电子设备。 电路板设置在壳体中。 第一非金属导电衬垫设置在电路板和壳体之间。 第一非金属导电垫的电位等于壳体的电位。 紧固元件将电路板和非金属导电垫紧固到壳体。

公开(公告)号：US20060272938A1

公开(公告)日：2006-12-07

申请号：US10908916

申请日：2005-06-01

申请人： Ta-Shuang Kuan ,  Yi-Ming Chang ,  Chia-Te Lin ,  Chia-Tsung Chan

发明人： Ta-Shuang Kuan ,  Yi-Ming Chang ,  Chia-Te Lin ,  Chia-Tsung Chan

IPC分类号： C23C14/00

CPC分类号： C23C14/34 ,  C23C14/225

摘要： The present invention provides a method of manufacturing an LC alignment film utilizing long-throw sputtering. The method includes putting a substrate on a substrate carrier in a chamber, utilizing high-density plasma to bombard a target over the substrate to produce sputtering species, and providing a bias voltage in the chamber. Nearly vertical directional sputtering species are deposited on the surface of the substrate to form an LC alignment film. The distance between the target and the substrate is more than 20 cm.

摘要翻译： 本发明提供利用长投射溅射制造LC取向膜的方法。 该方法包括将衬底放置在室中的衬底载体上，利用高密度等离子体在衬底上轰击靶以产生溅射物质，并在腔室中提供偏置电压。 几乎垂直的定向溅射物质沉积在衬底的表面上以形成LC取向膜。 靶和基片之间的距离大于20厘米。

公开(公告)号：US09142486B2

公开(公告)日：2015-09-22

申请号：US13554499

申请日：2012-07-20

申请人： Tsang-Yu Liu ,  Yi-Ming Chang ,  Tzu-Min Chen

发明人： Tsang-Yu Liu ,  Yi-Ming Chang ,  Tzu-Min Chen

IPC分类号： H01L23/48 ,  H01L23/16 ,  H01L21/56 ,  H01L27/146 ,  H01L23/31 ,  H01L23/58 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/16235 ,  H01L2924/00

摘要： An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

摘要翻译： 本发明的一个实施例涉及一种芯片封装及其制造方法，该芯片封装及其制造方法包括：包含芯片区域的半导体衬底和围绕芯片区域的外围焊盘区域，其中形成导电焊盘和暴露导电焊盘的通孔 外围垫区域; 覆盖半导体衬底的底表面和通孔的保护层; 形成在所述半导体衬底的上表面上的封装层; 以及形成在所述封装层和所述半导体基板之间的间隔层，其中所述芯片封装具有由所述半导体基板，所述保护层，所述封装层和所述间隔层的侧面构成的主侧面，并且其中所述主侧面 具有至少一个凹部。

公开(公告)号：US08785956B2

公开(公告)日：2014-07-22

申请号：US13560842

申请日：2012-07-27

申请人： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang ,  Hui-Ching Yang ,  Chiung-Lin Lai

发明人： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang ,  Hui-Ching Yang ,  Chiung-Lin Lai

IPC分类号： H01L33/00 ,  H01L21/00 ,  H01L33/52 ,  H01L27/146 ,  H01L23/00

CPC分类号： H01L27/14623 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L33/52 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的光电子器件; 设置在所述基板上的导电层，其中所述导电层电连接到所述光电子器件; 设置在所述基板和所述导电层之间的绝缘层; 设置在所述基板的第二表面上的第一遮光层; 以及第二遮光层，其设置在所述第一遮光层上并与所述第一遮光层直接接触，其中所述第一遮光层和所述第二遮光层之间的接触界面。

公开(公告)号：US20100212228A1

公开(公告)日：2010-08-26

申请号：US12424532

申请日：2009-04-15

申请人： Yi-Ming Chang ,  Min-Chun Chen

发明人： Yi-Ming Chang ,  Min-Chun Chen

IPC分类号： E05F11/24

CPC分类号： E05B65/006 ,  E05B17/0037 ,  E05B2015/0235 ,  G06F1/1616 ,  G06F1/1679

摘要： A fastening mechanism suitable for being assembled into a device having a housing is provided. The fastening mechanism includes a post, a latching element, at least a plunger assembly, and an operating element. The latching element has at least an opening, the plunger assembly is disposed at a side of the latching element, and the operating element is in contact with the latching element. The post passes through the opening and presses against the plunger assembly and the post is confined by the latching element when the operating element is in a locking position. The operating element drives the latching element to move horizontally relative to the latching element so as to release the post from confinement and the plunger assembly moves vertically relative to the latching element so as to push the post out of the opening when the operating element moves to an unlocking position.

摘要翻译： 提供一种适于组装成具有壳体的装置的紧固机构。 紧固机构包括柱，闩锁元件，至少一个柱塞组件和操作元件。 闩锁元件具有至少一个开口，柱塞组件设置在闩锁元件的一侧，并且操作元件与闩锁元件接触。 柱通过开口并压靠在柱塞组件上，当操作元件处于锁定位置时，该柱由锁定元件限制。 操作元件驱动闩锁元件相对于闩锁元件水平移动，以便将柱塞从限制释放，并且柱塞组件相对于闩锁元件垂直移动，以便当操作元件移动到 解锁位置

公开(公告)号：US20100142166A1

公开(公告)日：2010-06-10

申请号：US12368963

申请日：2009-02-10

申请人： Yi-Ming Chang ,  Yung-Chih Kuo ,  Chung-Teng Wu

发明人： Yi-Ming Chang ,  Yung-Chih Kuo ,  Chung-Teng Wu

IPC分类号： H05K5/00

CPC分类号： G06F1/1656 ,  G06F1/1616

摘要： An electronic device including a housing, a circuit board, a first non-metal conductive cushion and a fastening element is provided. The circuit board is disposed in the housing. The first non-metal conductive cushion is disposed between the circuit board and the housing. A potential of the first non-metal conductive cushion is equal to a potential of the housing. The fastening element fastens the circuit board and the non-metal conductive cushion to the housing.

摘要翻译： 提供了一种包括壳体，电路板，第一非金属导电衬垫和紧固元件的电子设备。 电路板设置在壳体中。 第一非金属导电衬垫设置在电路板和壳体之间。 第一非金属导电垫的电位等于壳体的电位。 紧固元件将电路板和非金属导电垫紧固到壳体。