公开(公告)号：US07406587B1

公开(公告)日：2008-07-29

申请号：US10210257

申请日：2002-07-31

Applicant: David X. Zhang ,  Kenneth C. Yeager

Inventor： David X. Zhang ,  Kenneth C. Yeager

IPC: G06F9/30

CPC classification number: G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

Abstract: A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique physical register is used to hold a result according to execution of the instruction. An indication is provided to the mapping table when the selected unique physical register contains the result. The result is then moved to a fixed status register. The selected unique physical register is then returned for later reuse and the next consecutive physical register is selected for the next instruction such that physical registers are used in order. An indication is provided for output to inform whether the result is in the selected unique physical register or has been moved to the fixed status register.

Abstract translation: 处理器包括用于缓冲指令的活动列表及其相关联的状态代码用于处理。 处理器中的映射表将与指令相关联的逻辑寄存器映射到多个唯一物理寄存器中的所选择的一个。 所选择的唯一物理寄存器用于根据指令的执行保存结果。 当所选择的唯一物理寄存器包含结果时，向映射表提供指示。 然后将结果移动到固定状态寄存器。 然后将所选择的唯一物理寄存器返回以供稍后重用，并且为下一个指令选择下一个连续的物理寄存器，以便按顺序使用物理寄存器。 提供了用于输出的指示以通知结果是否在所选择的唯一物理寄存器中或已被移动到固定状态寄存器。

公开(公告)号：US07007205B1

公开(公告)日：2006-02-28

申请号：US09788174

申请日：2001-02-15

Applicant: Kenneth C. Yeager ,  Steven T. Peltier ,  David X. Zhang

Inventor： Kenneth C. Yeager ,  Steven T. Peltier ,  David X. Zhang

IPC: G06F11/00

CPC classification number: G06F11/364

Abstract: An integrated circuit (10) includes a central processing unit (12), an instruction cache (14), a data cache (16), and a trace recorder. The central processing unit (12) interacts with the instruction cache (14) and the data cache (16) in order to execute instructions. Information passed between the central processing unit (12), the instruction cache (14), and the data cache (16) not normally available for external analysis may be captured by the trace recorder (20) in response to various triggering events. The information captured by the trace recorder (20) may subsequently be provided to external test equipment in order to analyze the operation of the central processing unit (12) for failure correction.

Abstract translation: 集成电路（10）包括中央处理单元（12），指令高速缓存（14），数据高速缓存（16）和跟踪记录器。 中央处理单元（12）与指令高速缓存（14）和数据高速缓冲存储器（16）交互以执行指令。 在跟踪记录器（20）响应于各种触发事件可以捕获在中央处理单元（12），指令高速缓存（14）和通常不可用于外部分析的数据高速缓存（16）之间传递的信息。 跟踪记录器（20）捕获的信息可以随后被提供给外部测试设备，以分析用于故障校正的中央处理单元（12）的操作。

公开(公告)号：US06738885B1

公开(公告)日：2004-05-18

申请号：US09788175

申请日：2001-02-15

Applicant: David X. Zhang ,  Kenneth C. Yeager ,  Steven T. Peltier

Inventor： David X. Zhang ,  Kenneth C. Yeager ,  Steven T. Peltier

IPC: G06F1200

CPC classification number: G06F11/3636 ,  G06F11/3476 ,  G06F2201/86

Abstract: An information capturing device (10) includes a controller (12) and a memory (14). The controller (12) partitions a memory space of the memory (14) into a plurality of memory blocks (20). The controller (12) controls the storage of received information into a first set (22) of the plurality of memory blocks (20). The controller (12) continues to store received information only in the first set (22) of the plurality of memory blocks (20) through reuse and recycle until a first triggering event occurs. In response to the first triggering event, the controller (12) halts the storage of received information in the first set (22) of the plurality of memory blocks (20) and begins storing received information in a second set (24) of the plurality of memory blocks (20). When the second set (24) of the plurality of memory blocks (24) has reached its storage capacity, the controller (12) begins storing received information in a third set (26) of the plurality of memory blocks (20). The controller (12) continues to store received information only in the third set (26) of the plurality of memory blocks (20) through reuse and recycle until a second triggering event occurs. Information pertaining to the first triggering event is maintained in the first set (22) and the second set (24) of the plurality of memory blocks (20).

Abstract translation: 信息捕获装置（10）包括控制器（12）和存储器（14）。 控制器（12）将存储器（14）的存储器空间分割成多个存储块（20）。 控制器（12）控制将接收的信息存储到多个存储器块（20）的第一组（22）中。 控制器（12）通过再利用和再循环继续将接收的信息仅存储在多个存储块（20）的第一组（22）中，直到发生第一触发事件。 响应于第一触发事件，控制器（12）停止在多个存储块（20）的第一组（22）中的接收信息的存储，并且开始将接收到的信息存储在多个存储块（20）的第二组（24）中 的存储器块（20）。 当多个存储块（24）中的第二组（24）达到其存储容量时，控制器（12）开始将接收的信息存储在多个存储块（20）的第三组（26）中。 控制器（12）通过再利用和再循环继续仅存储多个存储块（20）的第三组（26）中的接收信息，直到发生第二触发事件。 关于第一触发事件的信息被保持在多个存储块（20）的第一组（22）和第二组（24）中。

公开(公告)号：US06634011B1

公开(公告)日：2003-10-14

申请号：US09788195

申请日：2001-02-15

Applicant: Steven T. Peltier ,  David X. Zhang ,  Kenneth C. Yeager

Inventor： Steven T. Peltier ,  David X. Zhang ,  Kenneth C. Yeager

IPC: G06F1750

CPC classification number: G06F11/348

Abstract: An integrated circuit (10) includes a central processing unit (12), an instruction cache (14), a data cache, (16), and a trace recorder. The central processing unit (12) interacts with the instruction cache (14) and the data cache (16) in order to execute instructions. Profile information passed between the central processing unit (12), the instruction cache (14), and the data cache (16) not normally available for external analysis may be captured by the trace recorder (20) in response to various execution points in a program being executed by the central processing unit (12). The profile information captured by the trace recorder (20) may subsequently be provided to external analysis equipment in order to analyze the operation of the central processing unit (12) for study of program execution.

Abstract translation: 集成电路（ 10 ）包括中央处理单元（ 12 ），指令高速缓存（ 14 ），数据高速缓存（ 16 ）和跟踪记录器。 中央处理单元（ 12 ）与指令高速缓存（ 14 ）和数据高速缓存（ PDAT> 16 ）以执行指令。 在中央处理单元（ 12 ），指令高速缓存（ 14 ）和数据高速缓存（ 通常可用于外部分析的 16 ）可以由跟踪记录器（ 20 ）捕获，以响应各种执行点 在由中央处理单元（ 12 ）执行的程序中。 跟踪记录器（ 20 ）捕获的简档信息随后可以提供给外部分析设备，以便分析中央处理单元的操作（ 12 ）用于研究程序执行。

公开(公告)号：US06904501B1

公开(公告)日：2005-06-07

申请号：US10174391

申请日：2002-06-17

Applicant: David X. Zhang ,  Kenneth C. Yeager

Inventor： David X. Zhang ,  Kenneth C. Yeager

IPC: G06F12/12 ,  G06F12/00

CPC classification number: G06F12/125 ,  G06F12/126

Abstract: A cache memory includes a plurality of data memory blocks and a code memory block. Each data memory block has a plurality of storage locations and has a particular storage location identified by a same index value. The code memory block has a plurality of code values with a particular code value being associated with the same index value. The particular code value is operable to identify which ones of the particular storage locations associated with the same index value are locked to prevent alteration of contents therein. The particular code value is also operable to identify which particular storage location has been most recently used and which particular storage location has been least recently used of the particular storage locations associated with the same index value.

Abstract translation: 高速缓冲存储器包括多个数据存储块和代码存储块。 每个数据存储块具有多个存储位置，并且具有由相同索引值标识的特定存储位置。 代码存储器块具有多个代码值，其特定代码值与相同的索引值相关联。 特定代码值可操作以识别与相同索引值相关联的特定存储位置中的哪一个被锁定以防止其中的内容的改变。 特定代码值还可用于识别最近使用哪个特定存储位置以及哪个特定存储位置最近最近被用于与相同索引值相关联的特定存储位置。

公开(公告)号：US5978887A

公开(公告)日：1999-11-02

申请号：US813500

申请日：1997-03-07

Applicant: Kenneth C. Yeager

Inventor： Kenneth C. Yeager

IPC: G06F12/08

CPC classification number: G06F12/0851 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/1063

Abstract: A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilitates the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.

Abstract translation: 公开了具有复用输出和交替方式的双向高速缓冲存储器。 多路复用输出使得高速缓冲存储器能够用更少的读出放大器来进行更密集的封装和实现。 交替方式使两个不同的缓存访问模式。 根据第一访问模式，可以同时访问两个双字。 这种访问有助于将数据导入主存储器。 根据第二访问模式，可以同时访问相同位置但以不同方式的两个双字。 这样的访问有助于将特定单词加载到寄存器文件中。

公开(公告)号：US06266755B1

公开(公告)日：2001-07-24

申请号：US08772233

申请日：1996-12-23

Applicant: Kenneth C. Yeager

Inventor： Kenneth C. Yeager

IPC: G06F934

CPC classification number: G11C29/88 ,  G06F11/004 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/652

Abstract: A translation lookaside buffer for detecting and preventing conflicting virtual addresses from being stored therein is disclosed. Each entry in the buffer is associated with a switch which can be set and reset to enable and disable, respectively, a buffer entry. A switch associated with an existing entry will be reset if such entry conflicts with a new buffer entry.

Abstract translation: 公开了用于检测和防止存在冲突的虚拟地址的翻译后备缓冲器。 缓冲器中的每个条目与可以被设置和复位以分别启用和禁用缓冲器条目的开关相关联。 如果这样的条目与新的缓冲区条目冲突，则与现有条目关联的切换将被重置。

公开(公告)号：US08402225B2

公开(公告)日：2013-03-19

申请号：US12887374

申请日：2010-09-21

Applicant: Steven C. Miller ,  Martin M. Deneroff ,  Kenneth C. Yeager

Inventor： Steven C. Miller ,  Martin M. Deneroff ,  Kenneth C. Yeager

IPC: G06F13/20

CPC classification number: G06F12/0815 ,  G06F12/0808

Abstract: In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.

Abstract translation: 在计算系统中，通过选择用于第一存储器事务的多个一致性协议之一来执行高速缓存一致性。 多个一致性协议中的每一个具有可以应用于第一存储器事务的缓存数据的唯一的高速缓存状态集合。 通过应用多个相关协议中所选择的一个的一组缓存状态，在计算系统中的适当的高速缓存上执行高速缓存一致性。

公开(公告)号：US20110016277A1

公开(公告)日：2011-01-20

申请号：US12887374

申请日：2010-09-21

Applicant: Steven C. Miller ,  Martin M. Deneroff ,  Kenneth C. Yeager

Inventor： Steven C. Miller ,  Martin M. Deneroff ,  Kenneth C. Yeager

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0815 ,  G06F12/0808

Abstract: In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.

Abstract translation: 在计算系统中，通过选择用于第一存储器事务的多个一致性协议之一来执行高速缓存一致性。 多个一致性协议中的每一个具有可以应用于第一存储器事务的缓存数据的唯一的高速缓存状态集合。 通过应用多个相关协议中所选择的一个的一组缓存状态，在计算系统中的适当的高速缓存上执行高速缓存一致性。

公开(公告)号：US06918010B1

公开(公告)日：2005-07-12

申请号：US10272642

申请日：2002-10-16

Applicant: Kenneth C. Yeager

Inventor： Kenneth C. Yeager

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F9/30181 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/325 ,  G06F9/345 ,  G06F9/383 ,  G06F12/0862

Abstract: In prefetching cache lines from a main memory to a cache memory, an array of memory locations to be prefetched is determined and a base address indicating a highest address in the array is identified as well as a loop index used to point to the first address in the array. A prefetch index, which is the loop index plus a latency/transfer value, is used to prefetch memory locations as the array is processed. After a memory location is prefetched and initialized, the loop index and the prefetch index are incremented. The prefetch index is compared to a threshold value. If the prefetch index is less than the threshold value, then the next memory location in the array is prefetched and the prefetch index is again incremented and compared to the threshold value. If the prefetch index is equal to or greater than the threshold value, then the prefetch instruction is converted to a no operation instruction to prevent memory locations outside of the array from being prefetched during the processing of the array.

Abstract translation: 在将主存储器中的高速缓存行预取到高速缓冲存储器时，确定要预取的存储器位置的阵列，并且识别指示阵列中最高地址的基地址以及用于指向第一地址的循环索引 阵列。 预处理索引（循环索引加上延迟/传输值）用于在处理数组时对存储器位置进行预取。 在预取和初始化存储器位置之后，循环索引和预取索引被递增。 将预取索引与阈值进行比较。 如果预取索引小于阈值，则预取数组中的下一个存储器位置，并再次递增预取索引并将其与阈值进行比较。 如果预取索引等于或大于阈值，则将预取指令转换为无操作指令，以防止在阵列的处理期间预取数组外的存储器位置。