公开(公告)号：US12132493B2

公开(公告)日：2024-10-29

申请号：US17952863

申请日：2022-09-26

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Arashk Norouzpourshirazi ,  Ramin Zanbaghi ,  Stephen T. Hodapp ,  Christophe J. Amadi ,  Ravi K. Kummaraguntla ,  Dhrubajyoti Dutta

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: A system may include a sampling capacitor and a switch network. The switch network may include one or more first sampling switches electrically coupled to the sampling capacitor and configured to be activated during a first phase of a sampling cycle of the system and one or more second sampling switches electrically coupled to the sampling capacitor and configured to be activated during a second phase of the sampling cycle, wherein the switch network is configured to reset the sampling capacitor to a data-independent and/or signal-independent charge during a reset phase of the sampling cycle.

公开(公告)号：US10284217B1

公开(公告)日：2019-05-07

申请号：US15882640

申请日：2018-01-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Edmund Mark Schneider ,  Daniel J. Allen ,  Aniruddha Satoskar ,  Seyedeh Maryam Mortazavi Zanjani ,  Brian P. Chesney ,  John C. Tucker ,  Christophe J. Amadi

IPC: H03M1/18 ,  H04R3/04 ,  H04R3/02 ,  G10K11/16 ,  H03M3/00 ,  H03M1/00 ,  H03M1/06

Abstract: In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

公开(公告)号：US11652455B2

公开(公告)日：2023-05-16

申请号：US17173813

申请日：2021-02-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ravi K. Kummaraguntla ,  Christophe J. Amadi ,  John L. Melanson ,  Axel Thomsen ,  John C. Tucker ,  Eric J. King

IPC: H03F3/387 ,  G01R31/3842 ,  G01R31/40 ,  H03F3/181

CPC classification number: H03F3/387 ,  G01R31/3842 ,  G01R31/40 ,  H03F3/181 ,  H03F2200/03 ,  H03F2200/375

Abstract: A signal processing system may include a signal path and a chop management circuit. The signal path may comprise a chopper configured to chop a differential input signal to the signal path at a chopping frequency and a low-pass filter downstream of the chopper and configured to filter out intermodulation products of a direct current offset of the signal path and intermodulation products of an aggressor on the differential input signal in order to generate an output signal. The chop management circuit may be communicatively coupled to the chopper and configured to, based on operational parameters associated with the signal path, dynamically manage energy of one or more clock signals used to define the chopping frequency.