公开(公告)号：US11455002B1

公开(公告)日：2022-09-27

申请号：US17331967

申请日：2021-05-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil Whyte ,  Andy Brewster ,  Angus Black

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10

Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.

公开(公告)号：US11990896B2

公开(公告)日：2024-05-21

申请号：US17874357

申请日：2022-07-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Axel Thomsen ,  Eric J. King ,  Thomas H. Hoff ,  John L. Melanson ,  Angus Black ,  Ross C. Morgan ,  Malcolm Blyth

IPC: H03K17/687 ,  H02M3/158 ,  H02N2/00

CPC classification number: H03K17/6871 ,  H02M3/158 ,  H02N2/0075

Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers. A switching driver has first and second supply node for receiving supply voltages and includes an output bridge stage, a capacitor and a network of switches. The network of switches is operable in different switch states to provide different switching voltages to the output bridge stage. A controller is configured to control the switch state of the network of switches and a duty cycle of output switches of the output bridge stage based on an input signal to generate an output signal for driving the transducer.

公开(公告)号：US11228289B1

公开(公告)日：2022-01-18

申请号：US17000852

申请日：2020-08-24

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Angus Black ,  Hemant Shukla

IPC: H03F3/217 ,  H03G3/30 ,  H04R3/00

Abstract: This application describes an amplifier circuit (200) with a forward signal path with a class-D output stage (102) for generating a driving signal (Sout) based on a digital input signal (Sin). The amplifier has a first feedback path for providing a first digital feedback signal (Sfb1) based on the driving signal and a second feedback path for providing a second digital feedback signal (Sfb2) from a digital part of the forward signal path. The digital input signal (Sin) is combined with a selected feedback signal (Sfbs). The amplifier circuit is selectively operable in a first mode, in which the first feedback signal is used as the selected feedback signal, and in a second mode, in which the second feedback signal is used as the selected feedback signal. A calibration module (204) is operable to calibrate the first feedback path to reduce any DC offset when the amplifier circuit is operating in the second mode.