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公开(公告)号:US08618524B2
公开(公告)日:2013-12-31
申请号:US13029436
申请日:2011-02-17
申请人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号: H01L45/00
CPC分类号: H01L45/12 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1683
摘要: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要翻译: 存储器件包括相变元件,该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。
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2.
公开(公告)号:US08173990B2
公开(公告)日:2012-05-08
申请号:US12691549
申请日:2010-01-21
IPC分类号: H01L45/00
CPC分类号: H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要: An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译: 阵列包括:晶体管,包括第一端子,第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元,具有第一端和第二端,其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元,其中所述第三端连接到所述第二接触插塞。
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公开(公告)号:US20090230375A1
公开(公告)日:2009-09-17
申请号:US12049910
申请日:2008-03-17
申请人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号: H01L45/00 , H01L21/4763
CPC分类号: H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/148 , H01L45/1625 , H01L45/165
摘要: A semiconductor device is provided which includes a substrate having a dielectric layer formed thereon, a heating element formed in the dielectric layer, a phase change element formed on the heating element, and a conductive element formed on the phase change element. The phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline.
摘要翻译: 提供一种半导体器件,其包括其上形成有电介质层的衬底,形成在电介质层中的加热元件,形成在加热元件上的相变元件和形成在相变元件上的导电元件。 相变元件包括基本无定形的背景和有源区域,该有源区域能够改变无定形和晶态之间的相位。
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公开(公告)号:US20110140066A1
公开(公告)日:2011-06-16
申请号:US13029436
申请日:2011-02-17
申请人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号: H01L45/00
CPC分类号: H01L45/12 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1683
摘要: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要翻译: 存储器件包括相变元件,该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。
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公开(公告)号:US07893420B2
公开(公告)日:2011-02-22
申请号:US11858712
申请日:2007-09-20
申请人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号: H01L45/00
CPC分类号: H01L45/12 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1683
摘要: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要翻译: 存储器件包括相变元件,该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。
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6.
公开(公告)号:US07663134B2
公开(公告)日:2010-02-16
申请号:US11775741
申请日:2007-07-10
IPC分类号: H01L47/00
CPC分类号: H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要: An array includes a transistor cpmprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译: 阵列包括:晶体管,包括第一端子,第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元,具有第一端和第二端,其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元,其中所述第三端连接到所述第二接触插塞。
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公开(公告)号:US07642170B2
公开(公告)日:2010-01-05
申请号:US11864719
申请日:2007-09-28
申请人: Tzyh-Cheang Lee , Chun-Sheng Liang , Fu-Liang Yang
发明人: Tzyh-Cheang Lee , Chun-Sheng Liang , Fu-Liang Yang
IPC分类号: H01L21/20
CPC分类号: H01L45/1233 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1666
摘要: A method for constructing a phase change memory device includes forming a first dielectric layer on a substrate; forming a first conductive component in the first dielectric layer; forming a second dielectric layer over the first conductive component in the first dielectric layer; forming a conductive crown in the second dielectric layer, the conductive crown being in contact and alignment with the conductive component; depositing a third dielectric layer in the conductive crown; and forming a trench filled with chalcogenic materials having an amorphous phase and a crystalline phase programmable by controlling a temperature thereof to represent logic states, wherein the trench extends across the conductive crown, such that the trench is free from a rounded end portion caused by lithography during fabrication of the phase change memory device.
摘要翻译: 一种构造相变存储器件的方法包括:在衬底上形成第一电介质层; 在所述第一介电层中形成第一导电组分; 在所述第一介电层中的所述第一导电部件上形成第二电介质层; 在所述第二介电层中形成导电冠,所述导电冠与所述导电部件接触并对齐; 在导电冠中沉积第三电介质层; 并且形成填充有具有非晶相和结晶相的硫化物的沟槽,其可通过控制其温度来表示逻辑状态,其中所述沟槽延伸穿过所述导电冠,使得所述沟槽没有由光刻引起的圆形端部 在相变存储器件的制造过程中。
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公开(公告)号:US20090078924A1
公开(公告)日:2009-03-26
申请号:US11858712
申请日:2007-09-20
申请人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号: H01L45/00
CPC分类号: H01L45/12 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1683
摘要: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要翻译: 存储器件包括相变元件,该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。
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9.
公开(公告)号:US20100117045A1
公开(公告)日:2010-05-13
申请号:US12691549
申请日:2010-01-21
IPC分类号: H01L47/00
CPC分类号: H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要: An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译: 阵列包括:晶体管,包括第一端子,第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元,具有第一端和第二端,其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元,其中所述第三端连接到所述第二接触插塞。
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10.
公开(公告)号:US20090014836A1
公开(公告)日:2009-01-15
申请号:US11775741
申请日:2007-07-10
CPC分类号: H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要: An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译: 阵列包括:晶体管,包括第一端子,第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元,具有第一端和第二端,其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元,其中所述第三端连接到所述第二接触插塞。
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