-
公开(公告)号：US08667221B2
公开(公告)日：2014-03-04
申请号：US12099502
申请日：2008-04-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/128
摘要： An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be applied to make the streaming data become the next victim during a replacement.
摘要翻译： 提出了一种在存储器中检测流数据的装置。 在一个实施例中，装置对高速缓存行使用重用位和S位状态，其中S位状态指示高速缓存行中的数据是潜在的流数据。 为了提高高速缓存的效率，可以采用不同的措施来使流数据成为替换期间的下一个受害者。
-
2.发明授权Method and system to increase concurrency and control replication in a multi-core cache hierarchy 有权在多核缓存层次结构中增加并发性和控制复制的方法和系统公开(公告)号：US08171223B2
公开(公告)日：2012-05-01
申请号：US12315442
申请日：2008-12-03
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A directory of a private cache hierarchy is provided to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches from another private cache. This directory can be implemented in a system having a multi-core processor. Other embodiments are described.
摘要翻译： 提供专用高速缓存层级的目录以维持存储在高速缓存层次结构中的数据之间的一致性，其中目录是启用数据的并发缓存到高速缓存传输到来自另一专用高速缓存的两个专用高速缓存。 该目录可以在具有多核处理器的系统中实现。 描述其他实施例。
-
公开(公告)号：US08151012B2
公开(公告)日：2012-04-03
申请号：US12567638
申请日：2009-09-25
申请人： Changkyu Kim , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
发明人： Changkyu Kim , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
IPC分类号： G06F3/00
CPC分类号： G11C11/4082 , G06F1/3275 , G11C11/4085 , Y02D10/13 , Y02D10/14
摘要： Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
摘要翻译： 降低存储芯片能量消耗的方法，装置和系统，同时在执行任何工作负载的同时增加其效果带宽。 方法，设备和系统可以允许存储器芯片利用多个虚拟行缓冲器来响应包含在存储器阵列块中的数据的请求。 方法，装置和系统可以通过改变存储器阵列块和行缓冲器之间的数据传输大小来进一步消除或减少与将不需要的数据从存储器阵列块传送到行缓冲器相关联的成本。
-
公开(公告)号：US20100153649A1
公开(公告)日：2010-06-17
申请号：US12335381
申请日：2008-12-15
申请人： Wenlong Li , Yu Chen , Changkyu Kim , Christopher J. Hughes , Yen-Kuang Chen
发明人： Wenlong Li , Yu Chen , Changkyu Kim , Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0815
摘要： Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller is operable to determine a victim cache line for a cache set based at least in part on the number of misses.
摘要翻译： 呈现用于多核处理器的共享高速缓冲存储器的实施例。 在一个实施例中，高速缓存存储器包括一组采样高速缓存组和控制器，用于确定在采样高速缓存组组中出现的多少个未命中。 控制器可操作以至少部分地基于错失次数来确定用于高速缓存组的受害者高速缓存行。
-
公开(公告)号：US20100005241A1
公开(公告)日：2010-01-07
申请号：US12099502
申请日：2008-04-08
CPC分类号： G06F12/0897 , G06F12/128
摘要： An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be applied to make the streaming data become the next victim during a replacement.
摘要翻译： 提出了一种在存储器中检测流数据的装置。 在一个实施例中，装置对高速缓存行使用重用位和S位状态，其中S位状态指示高速缓存行中的数据是潜在的流数据。 为了提高高速缓存的效率，可以采用不同的措施来使流数据成为替换期间的下一个受害者。
-
6.发明申请Vector instructions to enable efficient synchronization and parallel reduction operations 有权用于实现高效同步和并行还原操作的矢量指令公开(公告)号：US20090249026A1
公开(公告)日：2009-10-01
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能 响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。 描述和要求保护其他实施例。
-
公开(公告)号：US08478941B2
公开(公告)日：2013-07-02
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
-
公开(公告)号：US20120290799A1
公开(公告)日：2012-11-15
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译： 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。
-
公开(公告)号：US20110138122A1
公开(公告)日：2011-06-09
申请号：US12630826
申请日：2009-12-03
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译： 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。
-
10.发明申请Increasing concurrency and controlling replication in a multi-core cache hierarchy 有权在多核缓存层次结构中增加并发性并控制复制公开(公告)号：US20100138607A1
公开(公告)日：2010-06-03
申请号：US12315442
申请日：2008-12-03
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： In one embodiment, the present invention includes a directory of a private cache hierarchy to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括专用高速缓存层级的目录，以保持存储在高速缓存层级中的数据之间的一致性，其中目录是启用数据到两个私有高速缓存的缓存到高速缓存的传输。 描述和要求保护其他实施例。
-
-
-
-
-
-
-
-
-
搜索结果
77 条记录 (耗时 0.024 秒)
