公开(公告)号：US20130140525A1

公开(公告)日：2013-06-06

申请号：US13308997

申请日：2011-12-01

Applicant: Chi-Ming CHEN ,  Po-Chun LIU ,  Hung-Ta LIN ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ho-Yung David HWANG

Inventor： Chi-Ming CHEN ,  Po-Chun LIU ,  Hung-Ta LIN ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ho-Yung David HWANG

IPC: H01L29/205 ,  H01L21/20

CPC classification number: C30B23/025 ,  C30B25/183 ,  C30B29/403 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/12 ,  H01L33/30 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/32341 ,  H01S2301/173

Abstract: A semiconductor structure includes a silicon substrate; more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer of the group III-V compound is separated by an interlayer.

Abstract translation: 半导体结构包括硅衬底; 在硅衬底顶上有III-Ⅴ族（Ⅴ-Ⅴ）族化合物半导体的多层体积层; 并且III-V族化合物的每个本体层被中间层分离。

公开(公告)号：US20130112939A1

公开(公告)日：2013-05-09

申请号：US13290534

申请日：2011-11-07

Applicant: Chi-Ming CHEN ,  Po-Chun LIU ,  Hung-Ta LIN ,  Chin-Cheng CHANG ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ho-Yung David HWANG

Inventor： Chi-Ming CHEN ,  Po-Chun LIU ,  Hung-Ta LIN ,  Chin-Cheng CHANG ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ho-Yung David HWANG

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L33/007 ,  C30B25/183 ,  C30B29/403 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/66462

Abstract: A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.

Abstract translation: 电路结构包括衬底和衬底上的图案化电介质层。 图案化电介质层包括多个通孔; 和III族V族（III-V）族化合物半导体层。 III-V族化合物半导体层包括通孔中的第一层，第一层上的第二层和电介质层，以及在第二层上的体层。

公开(公告)号：US20140197418A1

公开(公告)日：2014-07-17

申请号：US13743045

申请日：2013-01-16

Applicant: Chi-Ming CHEN ,  Po-Chun LIU ,  Chung-Yi YU ,  Chia-Shiung TSAI

Inventor： Chi-Ming CHEN ,  Po-Chun LIU ,  Chung-Yi YU ,  Chia-Shiung TSAI

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L21/02507 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.

Abstract translation: 半导体结构包括衬底，在衬底上的第一III-V化合物层，在第一III-V化合物层上的一组或多组III-V化合物层，在一个或多个组上的第二III-V化合物层 的III-V化合物层，以及在第二III-V化合物层上的活性层。 第一III-V族化合物层具有第一种掺杂。 一组或多组III-V化合物层中的每一个在下III-V化合物层上包括下III-V化合物层和上III-V化合物层。 具有第一类掺杂的上III-V化合物层和下III-V族化合物层是至少一种未掺杂的，无意掺杂的具有第二类型掺杂或掺杂具有第二类掺杂的至少一种。 第二III-V族化合物层是未掺杂的或无意掺杂的，具有第二种掺杂。

公开(公告)号：US20130099243A1

公开(公告)日：2013-04-25

申请号：US13277692

申请日：2011-10-20

Applicant: Chi-Ming CHEN ,  Po-Chun LIU ,  Hung-Ta LIN ,  Chin-Cheng CHANG ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ho-Yung David HWANG

Inventor： Chi-Ming CHEN ,  Po-Chun LIU ,  Hung-Ta LIN ,  Chin-Cheng CHANG ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ho-Yung David HWANG

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7787

Abstract: A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.

Abstract translation: 电路结构包括衬底，未掺杂的氮化铝的成核层，包含铝，镓，氮，硅和氧中的一种的梯度缓冲层和p型导电掺杂剂，包含镓，氮，一个 的硅和氧，以及没有铝的p型导电掺杂物，以及未分级缓冲层上的未掺杂氮化镓的体层。 分级缓冲层和未分级缓冲层中的各种掺杂剂增加了电阻率并导致具有本质上平衡的导电性的层。

公开(公告)号：US20090085050A1

公开(公告)日：2009-04-02

申请号：US11948464

申请日：2007-11-30

Applicant: Yih-Der GUO ,  Jenq-Dar TSAY ,  Po-Chun LIU

Inventor： Yih-Der GUO ,  Jenq-Dar TSAY ,  Po-Chun LIU

IPC: H01L21/28 ,  F21V7/00 ,  H05K3/02 ,  F21V21/00 ,  H05K3/00 ,  H01L33/00

CPC classification number: H05K3/4007 ,  H01L33/486 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K1/0306 ,  H05K1/053 ,  H05K1/111 ,  H05K1/113 ,  H05K2201/09045 ,  H05K2201/10106 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: An island submount used for carrying at least one light-emitting element having at least one electrical contact. The island submount includes a substrate, at least one island structure having a top surface and an inclined surface, and a conductive layer. The island structure is located on the substrate and corresponds to the electrical contact. The conductive layer is formed on the surface of the island structure and at least covers the top surface, so as to be electrically connected with the electrical contact. The island submount is capable of enhancing the light extraction efficiency of the light-emitting element, and avoids the energy loss due to re-absorption when the light emerging from below the light-emitting element is reflected back to the light-emitting element.

Abstract translation: 用于承载至少一个具有至少一个电触头的发光元件的岛基座。 岛基座包括基板，具有顶表面和倾斜表面的至少一个岛结构和导电层。 岛结构位于基板上并对应于电接触。 导电层形成在岛状结构的表面上，并且至少覆盖顶表面，从而与电触点电连接。 岛基座能够增强发光元件的光提取效率，并且当从发光元件下方出射的光被反射回发光元件时，可以避免由于再吸收而导致的能量损失。

公开(公告)号：US20120159187A1

公开(公告)日：2012-06-21

申请号：US13034713

申请日：2011-02-25

Applicant: Po-Chun LIU ,  Hsie-Chia CHANG ,  Chen-Yi LEE

Inventor： Po-Chun LIU ,  Hsie-Chia CHANG ,  Chen-Yi LEE

IPC: G06F12/14

CPC classification number: G06F21/755

Abstract: An electronic device and a method for protecting against a differential power analysis attack are disclosed herein. The electronic device includes an encryption/decryption unit, a random number generator and a countermeasure circuit. The encryption/decryption unit can provide an enable signal when encrypting or decrypting more bits of data. The random number generator can generate random data. When receiving the enable signal, the countermeasure circuit can operate according to the bits of data and the random data.

Abstract translation: 本文公开了一种用于防止差分功率分析攻击的电子设备和方法。 电子设备包括加密/解密单元，随机数发生器和对策电路。 加密/解密单元可以在加密或解密更多数据位时提供使能信号。 随机数生成器可以生成随机数据。 当接收到使能信号时，对策电路可以根据数据位和随机数据进行操作。