摘要:
Apparatus and a method for determining the onset of an interarterial blood pressure pulse and measuring the time delay preceding the onset from the corresponding electrical heartbeart triggering signal wherein the blood pressure pulse is converted to an electrical input signal which is split into two identical components, one being delayed in time, inverted and amplified after which it is added to the other. A timer measures the duration between the electrical heartbeat actuating signal and the point at which the sum of the blood pressure component signals reaches a peak and subtracts from that result the time delay applied to the one component to yield the electromechanical interval between the electrical heartbeat signal and onset of the blood pressure pulse.
摘要:
A typical fluid mixer of the heavy-duty type conventionally has a compartment including walls, one of which has a circular opening through which a motor-driven shaft extends. An external seal is provided for sealing the shaft-to-wall junction against fluid leakage. When it becomes necessary to replace the seal, the compartment must be drained to avoid leakage at the opening. The present invention provides an internal seal that is normally spaced along the shaft away from the wall but which can be forcibly moved toward and compressed against the wall and thus seal the shaft and opening and preventing leakage during repairs and consequently eliminating emptying the tank. The interior seal is supported by a movable carrier, and reversible force-exerting mechanism extending exteriorly of the compartment is employed to move the carrier and interior seal into and out of its interior sealing position. In a preferred embodiment, the force-exerting mechanism includes one or more jack screws.
摘要:
An apparatus and method for recording and reproducing extended periods of video information on a longitudinal tape recorder without losing synchronism or image quality. The composite video signal, and synchronization signals extracted therefrom, are recorded in spatial registry on separate channels of a longitudinal tape recorder/reproducer. Vertical synchronization quality is maintained by recording on a channel capable of low frequency processing. Upon reproduction all synchronization, including mixing with supplemental video sources, is synchronized to the recorded master video synchronization and blanking signals. Video display at other than normal speeds is temporally synchronized from the slower tape speed. An X-Y monitor driven by vertical and horizontal sweep signals synchronized to the corresponding recorded synchronization signals generates a video presentation without repeated or omitted frames.
摘要:
A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.
摘要:
A pipe bending system employing a sensing and indicating system that provides feedback to an operator regarding the position of components of the pipe bending system, such as the pin-up shoe and the stiffback. Apparatus for retrofitting a sensing and indicating system to existing pipe bending apparatus.
摘要:
An intrauterine catheter device for monitoring fetal and/or maternal heart rate, including an elongate housing having proximal and distal portions, an array of ECG electrodes on the distal portion and one or more acoustic or other mechanical sensors on the distal portion. A pressure transducer may also be provided on the distal portion. Processor circuitry compares the ECG signal with the output signal of the acoustic sensor to derive fetal and/or maternal heart rate. An intrauterine catheter device is also provided, including a reference electrode on its distal portion, and an array of active electrodes spaced apart from one another on the distal portion. The device may also include a pressure transducer on the distal portion and processor circuitry coupled to the array of active electrodes and/or to the reference electrode for deriving fetal ECG from signals produced by the array of active electrodes. Alternatively, the array of electrodes and acoustic sensors may be provided on a flexible pad that may be secured to the abdomen of a pregnant mother. An intrauterine catheter device is also provided, including a plurality of lumens communicating with a differential pressure transducer provided on its distal portion, and having a zeroing switch on its proximal portion for resetting the pressure transducer in situ.
摘要:
A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
摘要:
A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
摘要:
A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.
摘要:
A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.