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    DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME
    1.
    发明申请
    DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME 有权
    数据压缩装置，其操作方法和包括其的数据处理装置

    公开(公告)号：US20140152475A1

    公开(公告)日：2014-06-05

    申请号：US14173086

    申请日：2014-02-05

    申请人： Kyoung Lae CHO ,  Chan Ho YOON ,  Jun Jin KONG ,  Pil Sang YOON

    发明人： Kyoung Lae CHO ,  Chan Ho YOON ,  Jun Jin KONG ,  Pil Sang YOON

    IPC分类号： H03M7/30

    CPC分类号： H03M7/30 ,  H03M7/6088

    摘要： A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

    摘要翻译： 操作数据压缩装置的方法包括使用分析器分析数据并产生分析结果，同时数据由输入缓冲器缓冲，并根据分析结果选择性地压缩缓冲的数据。 数据压缩装置包括数据模式分析器，被配置为分析发送到输入缓冲器的数据，并且基于数据的分析生成分析代码; 以及数据压缩管理器，被配置为基于分析代码选择性地压缩输入缓冲器中的数据。

    MEMORY SYSTEM WITH ERROR CORRECTION DECODER ARCHITECTURE HAVING REDUCED LATENCY AND INCREASED THROUGHPUT
    2.
    发明申请
    MEMORY SYSTEM WITH ERROR CORRECTION DECODER ARCHITECTURE HAVING REDUCED LATENCY AND INCREASED THROUGHPUT 有权
    具有错误校正解码器结构的存储器系统具有减少的延迟和增加的延迟

    公开(公告)号：US20090070656A1

    公开(公告)日：2009-03-12

    申请号：US12191458

    申请日：2008-08-14

    申请人： Nam Phil JO ,  Jun Jin KONG ,  Chan Ho YOON ,  Dong Hyuk CHAE ,  Kyoung Lae CHO

    发明人： Nam Phil JO ,  Jun Jin KONG ,  Chan Ho YOON ,  Dong Hyuk CHAE ,  Kyoung Lae CHO

    IPC分类号： G11C29/04 ,  G06F11/07

    CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

    DATA STORAGE DEVICES, DATA PROCESSING SYSTEMS HAVING THE SAME, METHODS OF OPERATING AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    DATA STORAGE DEVICES, DATA PROCESSING SYSTEMS HAVING THE SAME, METHODS OF OPERATING AND METHODS OF MANUFACTURING THE SAME 审中-公开
    数据存储设备，具有该数据存储设备的数据处理系统，操作方法及其制造方法

    公开(公告)号：US20160274794A1

    公开(公告)日：2016-09-22

    申请号：US15069568

    申请日：2016-03-14

    申请人： Chan Ho YOON

    发明人： Chan Ho YOON

    IPC分类号： G06F3/06 ,  G06F12/10

    CPC分类号： G06F3/0605 ,  G06F3/064 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/261 ,  G06F2212/7201 ,  G06F2212/7208

    摘要： A scale-out device to control a group of non-volatile memory devices from among a plurality of non-volatile memory devices at a data storage device, includes a buffer and a scale-out controller. The buffer is configured to store address mapping information for the group of non-volatile memory devices, the group of non-volatile memory devices being a portion of the plurality of non-volatile memory devices at the data storage device. The scale-out controller is configured to control operation of only the group of non-volatile memory devices according to the address mapping information stored at the buffer.

    摘要翻译： 用于在数据存储设备处从多个非易失性存储器设备中控制一组非易失性存储器设备的横向扩展设备包括缓冲器和横向扩展控制器。 缓冲器被配置为存储用于该组非易失性存储器设备的地址映射信息，该组非易失性存储器设备是数据存储设备处的多个非易失性存储器设备的一部分。 横向扩展控制器被配置为根据存储在缓冲器处的地址映射信息来控制仅一组非易失性存储器件的操作。