-
1.发明授权公开(公告)号：US06596981B1
公开(公告)日：2003-07-22
申请号：US10047484
申请日：2002-01-14
IPC分类号： H01L3100
CPC分类号： H01L27/1446 , G01J1/0488 , G01J1/4204 , G01J1/4228 , G01J3/2803 , G01J2001/4247 , H01L31/02164 , H01L31/103
摘要： A monolithic optical detector for determining spectral content of an incident light includes at least a first and second well in a substrate, the second well formed proximate the first well. The first well is configured to be exposed to incident light and for generating a first photocurrent as a function of the incident light. The second well is configured to be shielded from the incident light and for generating a second photocurrent as a function of the incident light. Lastly, a processing and control unit, responsive to the first and second photocurrents, determines an indication of spectral content of the incident light. A method and device parameter controller are also disclosed.
摘要翻译： 用于确定入射光的光谱含量的单片光学检测器包括衬底中的至少第一阱和第二阱，第二阱在第一阱附近形成。 第一阱被配置为暴露于入射光并用于产生作为入射光的函数的第一光电流。 第二阱被配置为与入射光屏蔽，并且用于产生作为入射光的函数的第二光电流。 最后，响应于第一和第二光电流的处理和控制单元确定入射光的光谱含量的指示。 还公开了一种方法和设备参数控制器。
-
2.发明授权公开(公告)号：US08274051B1
公开(公告)日：2012-09-25
申请号：US13097420
申请日：2011-04-29
申请人： Cecil Aswell , Eugene G. Dierschke
发明人： Cecil Aswell , Eugene G. Dierschke
CPC分类号： G01J3/524 , G01J1/0488 , G01J1/4204 , G01J1/4228 , G01J3/0262 , G01J3/513 , H01L27/14621 , H01L27/14623 , H01L31/02162
摘要： Semiconductor structures for optoelectronic sensors with an infrared (IR) blocking filter and methods for using such sensors with post-detection compensation for IR content that passes through the IR blocking filter are provided herein.
摘要翻译： 本文提供了具有红外（IR）阻挡滤波器的光电传感器的半导体结构以及使用这种传感器的方法，该传感器具有通过IR阻挡滤波器的IR内容的后检测补偿。
-
公开(公告)号：US5594376A
公开(公告)日：1997-01-14
申请号：US317674
申请日：1994-10-05
申请人： Ken McBride , Cecil Aswell
发明人： Ken McBride , Cecil Aswell
摘要： A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances. A three input phase detector is coupled to a fixed delay line and to either the series terminated transmission line system or the Thevenin terminated transmission line system for eliminating phase shifts of the clock signals between the different loads.
摘要翻译： 时钟去歪斜设备使用串行终端单传输线路系统或Th + E，acu e + EE静电放电终端双传输线路系统，将时钟信号传送到负载。 实现了多个串联终止的时钟去歪斜设备，每个负载一个，使得时钟信号被同时传送到耦合到时钟信号的所有负载。 每个系列时钟去偏移装置具有与其耦合的传输线具有相同阻抗值的单个终端电阻。 每个Th + E，acu e + EE静电放电终端系统都有一个分压电阻网络。 可以调整每个系列时钟去偏移装置内的可变延迟线，使得每个负载同时接收时钟信号。 可编程输出驱动器阻抗网络可用于串联端接时钟反相校正系统的单线终端电阻，以便串联端接时钟去偏置设备可与具有不同线路阻抗的传输线路一起使用。 三输入相位检测器耦合到固定延迟线以及串联端接传输线系统或Th + E，acu e + EE venin终端传输线系统，以消除不同负载之间的时钟信号的相移。
-
公开(公告)号：US07620291B1
公开(公告)日：2009-11-17
申请号：US11391113
申请日：2006-03-28
申请人： Cecil Aswell
发明人： Cecil Aswell
IPC分类号： G02B6/00
CPC分类号： G01D18/004
摘要： A circuit for calibrating optoelectronic devices automatically trims a light sensor based upon a known light condition.
摘要翻译： 用于校准光电装置的电路基于已知的光条件自动修整光传感器。
-
公开(公告)号：US06570916B1
公开(公告)日：2003-05-27
申请号：US08811414
申请日：1997-03-04
IPC分类号： H03H740
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0812 , H04L7/0331 , H04L25/03885
摘要： A timing based adaptive equalization circuit (10) dynamically monitors a signal received at an input terminal (16) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit (26) centers the transition of the equalized signal in a delay line circuit (31). An analog delay locked loop circuit (29) provides a fixed throughput time for matching delay elements of delay line circuits (31, 41 and 51) in the adaptive equalization circuit (10). Timing signals propagating in the delay line circuits (31, 41 and 51) are stored in sampler circuits (36, 46 and 56). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits (46 and 56).
摘要翻译： 基于定时的自适应均衡电路（10）动态地监视在输入端（16）处接收到的信号，并通过调整增加或减少信号均衡的均衡值来补偿信号传输中的衰减损耗。 数字锁相环控制电路（26）使均衡信号在延迟线电路（31）中的转变居中。 模拟延迟锁定环电路（29）为自适应均衡电路（10）中的延迟线路电路（31,41和51）的延迟元件的匹配提供固定的吞吐时间。 在延迟线电路（31,41和51）中传播的定时信号被存储在采样器电路（36,46和56）中。 基于采样器电路（46和56）中的特定存储元件的存储逻辑值来调整用于均衡输入信号的均衡值。
-
6.发明授权
公开(公告)号：US5267269A
公开(公告)日：1993-11-30
申请号：US754604
申请日：1991-09-04
申请人： Cheng-chung Shih , Haim Shafir , Stefan M. Wurster , Cecil Aswell , Daniel L. Ray , Joseph E. Heideman
发明人： Cheng-chung Shih , Haim Shafir , Stefan M. Wurster , Cecil Aswell , Daniel L. Ray , Joseph E. Heideman
CPC分类号： H04L25/03866 , H04L25/08 , H04L25/4904
摘要： A data communication system employing predetermined equalized waveforms for transmit equalization is disclosed. Serial NRZ data is received from a network controller and utilized to select from memory its equivalent as predistorted and filtered Manchester encoded data. Predetermined waveforms in memory are representative of the analog waveform produced when predistorted digital Manchester encoded data is passed through a high order transmit filter. Data from memory drives a digital to analog converter (DAC) to reconstruct the waveforms into analog form. A line driver having an integrated single pole low pass filter impresses the equalized waveform on to the transmission line.
摘要翻译： 公开了一种采用预定均衡波形进行发送均衡的数据通信系统。 从网络控制器接收串行NRZ数据，并用于从存储器中选择其等同物作为预失真和滤波的曼彻斯特编码数据。 存储器中的预定波形表示当预失真数字曼彻斯特编码数据通过高阶发射滤波器时产生的模拟波形。 来自存储器的数据驱动数模转换器（DAC），将波形重建为模拟形式。 具有集成单极低通滤波器的线路驱动器将均衡波形印在传输线上。
-
公开(公告)号：US07019589B1
公开(公告)日：2006-03-28
申请号：US10823613
申请日：2004-04-14
IPC分类号： H03F1/36
CPC分类号： H03F1/34
摘要： A transimpedance amplifier includes a first amplifier, a first MOS resistor device and a first voltage divider circuit. The source terminal of the first MOS resistor device is coupled to the first amplifier inverting input. The voltage divider circuit is coupled between the first amplifier output and the non-inverting input. The output of the first voltage divider is coupled to the first MOS resistor drain terminal. A second amplifier, second MOS resistor device and a second voltage divider circuit is also provided. The output of the second amplifier is coupled to the gate terminal of the first MOS resistor device. The gate terminal of the second MOS resistor device is coupled to the second amplifier output. The drain terminal of the second MOS resistor device is coupled to the second amplifier non-inverting input. The second voltage divider circuit is coupled between the first amplifier output and the second MOS resistor device source terminal, and has an output coupled to the second amplifier inverting input.
摘要翻译： 跨阻放大器包括第一放大器，第一MOS电阻器件和第一分压器电路。 第一MOS电阻器件的源极端子耦合到第一放大器反相输入端。 分压器电路耦合在第一放大器输出和非反相输入之间。 第一分压器的输出耦合到第一MOS电阻漏极端子。 还提供了第二放大器，第二MOS电阻器件和第二分压器电路。 第二放大器的输出耦合到第一MOS电阻器件的栅极端子。 第二MOS电阻器件的栅极端子耦合到第二放大器输出端。 第二MOS电阻器件的漏极端子耦合到第二放大器非反相输入端。 第二分压器电路耦合在第一放大器输出端和第二MOS电阻器件源极端子之间，并且具有耦合到第二放大器反相输入端的输出端。
-
公开(公告)号：US5661427A
公开(公告)日：1997-08-26
申请号：US317675
申请日：1994-10-05
申请人： Ken McBride , Cecil Aswell
发明人： Ken McBride , Cecil Aswell
CPC分类号： H03K5/15046 , H03K5/14
摘要： A series clock deskewing apparatus uses a series terminated single transmission line system to deliver a clock signal to a load. A plurality of series clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads simultaneously. Each series clock deskewing apparatus has a single series termination resistor with the same impedance value as the transmission line to which it is coupled. For each load, the clock signal travels the transmission line from a clock generator to the load and is simultaneously applied to the deskewing apparatus. A clock signal is reflected at the load back to the deskewing apparatus. The roundtrip transit time is determined by the deskewing apparatus which causes an appropriate delay to adjust each clock signal to arrive synchronously at all the loads. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.
摘要翻译： 系列时钟去歪斜设备使用串行终端单传输线路系统向时钟信号发送一个负载。 实现了多个串联时钟去歪斜设备，每个负载一个，从而同时将时钟信号传送到所有负载。 每个系列时钟去偏移装置具有与其耦合的传输线具有相同阻抗值的单个串联终端电阻。 对于每个负载，时钟信号将传输线从时钟发生器传送到负载，同时被施加到去歪斜设备。 时钟信号在负载反射回到去歪斜设备。 往返通行时间由去歪斜装置确定，其导致适当的延迟来调整每个时钟信号以在所有负载下同步到达。 可编程输出驱动器阻抗网络可用于串行端接时钟的单线终端电阻，可与具有不同线路阻抗的传输线一起使用。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.016 秒)
