-
公开(公告)号：US11848045B2
公开(公告)日：2023-12-19
申请号：US17396688
申请日：2021-08-07
发明人： Weibing Shang , Jixing Chen , Xianjun Wu
IPC分类号： G11C7/12 , G11C11/4091 , G11C11/4096 , G11C11/4094 , G11C7/10 , G11C11/4093 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/1048 , G11C7/1078 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.
-
公开(公告)号：US12131059B2
公开(公告)日：2024-10-29
申请号：US17855848
申请日：2022-07-01
发明人： Xianjun Wu , Weibing Shang
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： Disclosed are a data writing circuit, a data writing method, and a memory. The data writing circuit includes: a delay generation circuit, configured to generate a sub-grab signal of each storage area based on an initial grab signal and data transmission delay of each storage area, and generate a grab enable signal based on all of the sub-grab signals. A time interval between the time that each storage area receives data transmitted by a global data line and the time of receiving a column selection signal meets a preset range. A read-write control circuit writes data on a data bus into the global data line based on the grab enable signal. The global data line transmits the data to the storage area by using a column decoding circuit based on the column selection signal, so as to optimize tCCD of DRAM.
-
公开(公告)号：US12009024B2
公开(公告)日：2024-06-11
申请号：US17810596
申请日：2022-07-02
发明人： Xianjun Wu , Weibing Shang
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/4096
CPC分类号： G11C11/4076 , G11C11/4085 , G11C11/4096
摘要： A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.
-
公开(公告)号：US20240265952A1
公开(公告)日：2024-08-08
申请号：US17796745
申请日：2022-04-18
发明人： Xianjun Wu , Weibing Shang , Xiaoqing Shi
CPC分类号： G11C7/08 , G11C7/1096
摘要： The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.
-
公开(公告)号：US20240079038A1
公开(公告)日：2024-03-07
申请号：US18180038
申请日：2023-03-07
发明人： Zhonglai Liu , Xianjun Wu , Anping Qiu
摘要： The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.
-
公开(公告)号：US11676642B2
公开(公告)日：2023-06-13
申请号：US17405107
申请日：2021-08-18
发明人： Weibing Shang , Fengqin Zhang , Kangling Ji , Kai Tian , Xianjun Wu
IPC分类号： G11C5/06 , G11C5/14 , G11C5/02 , H01L23/528
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , H01L23/5286
摘要： A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.015 秒)
