公开(公告)号：US07952694B2

公开(公告)日：2011-05-31

申请号：US12887829

申请日：2010-09-22

Applicant: Bradley J. Howard ,  Eric Pape ,  Siwen Li

Inventor： Bradley J. Howard ,  Eric Pape ,  Siwen Li

IPC: G01J3/30 ,  G01N27/04

CPC classification number: H01J37/32642 ,  H01J37/32935 ,  H01J37/32972 ,  H01J37/3299

Abstract: A disclosed device comprises an edge bonding seal configured to be mounted to an edge bead of the electrostatic chuck. The edge bonding seal includes a monitoring layer comprised of a first material configured to emit a species capable of being optically monitored. The edge bonding seal further includes an edge bonding layer configured to be interspersed at least between the monitoring layer and the plasma environment. The edge bonding layer is comprised of a second material susceptible to erosion due to reaction with the plasma environment and configured to expose the monitoring layer to the plasma environment upon sufficient exposure to the plasma environment.

Abstract translation: 所公开的装置包括构造成安装到静电卡盘的边缘珠缘上的边缘接合密封件。 边缘接合密封件包括由构造成发射能够进行光学监测的物质的第一材料构成的监测层。 边缘接合密封件还包括边缘粘合层，其被配置为至少散布在监测层和等离子体环境之间。 边缘粘合层由与等离子体环境的反应易受侵蚀的第二材料组成，并且被配置为在充分暴露于等离子体环境时将监测层暴露于等离子体环境。

公开(公告)号：US07884925B2

公开(公告)日：2011-02-08

申请号：US12126625

申请日：2008-05-23

Applicant: Bradley J. Howard ,  Eric Pape ,  Siwen Li

Inventor： Bradley J. Howard ,  Eric Pape ,  Siwen Li

IPC: G01J3/30 ,  G01N27/04

CPC classification number: H01J37/32642 ,  H01J37/32935 ,  H01J37/32972 ,  H01J37/3299

Abstract: A disclosed device comprises an edge bonding seal configured to be mounted to an edge bead of the electrostatic chuck. The edge bonding seal includes a monitoring layer comprised of a first material configured to either emit a species capable of being optically monitored or having an electrical resistance value capable of being monitored, or both. The edge bonding seal further includes an edge bonding layer configured to be interspersed at least between the monitoring layer and the plasma environment. The edge bonding layer is comprised of a second material susceptible to erosion due to reaction with the plasma environment and configured to expose the monitoring layer to the plasma environment upon sufficient exposure to the plasma environment.

Abstract translation: 所公开的装置包括构造成安装到静电卡盘的边缘珠缘上的边缘接合密封件。 边缘接合密封件包括由第一材料构成的监测层，该第一材料被配置为发射能够被光学监测的物质或具有能够被监测的电阻值，或两者。 边缘接合密封件还包括边缘粘合层，其被配置为至少散布在监测层和等离子体环境之间。 边缘粘合层由与等离子体环境的反应易受侵蚀的第二材料组成，并且被配置为在充分暴露于等离子体环境时将监测层暴露于等离子体环境。

公开(公告)号：US20110007303A1

公开(公告)日：2011-01-13

申请号：US12887829

申请日：2010-09-22

Applicant: Bradley J. Howard ,  Eric Pape ,  Siwen Li

Inventor： Bradley J. Howard ,  Eric Pape ,  Siwen Li

IPC: G01N21/00

CPC classification number: H01J37/32642 ,  H01J37/32935 ,  H01J37/32972 ,  H01J37/3299

Abstract: A disclosed device comprises an edge bonding seal configured to be mounted to an edge bead of the electrostatic chuck. The edge bonding seal includes a monitoring layer comprised of a first material configured to emit a species capable of being optically monitored. The edge bonding seal further includes an edge bonding layer configured to be interspersed at least between the monitoring layer and the plasma environment. The edge bonding layer is comprised of a second material susceptible to erosion due to reaction with the plasma environment and configured to expose the monitoring layer to the plasma environment upon sufficient exposure to the plasma environment.

Abstract translation: 所公开的装置包括构造成安装到静电卡盘的边缘珠缘上的边缘接合密封件。 边缘接合密封件包括由构造成发射能够进行光学监测的物质的第一材料构成的监测层。 边缘接合密封件还包括边缘粘合层，其被配置为至少散布在监测层和等离子体环境之间。 边缘粘合层由与等离子体环境的反应易受侵蚀的第二材料组成，并且被配置为在充分暴露于等离子体环境时将监测层暴露于等离子体环境。

公开(公告)号：US20090290145A1

公开(公告)日：2009-11-26

申请号：US12126625

申请日：2008-05-23

Applicant: Bradley J. Howard ,  Eric Pape ,  Siwen Li

Inventor： Bradley J. Howard ,  Eric Pape ,  Siwen Li

IPC: G01N21/63

CPC classification number: H01J37/32642 ,  H01J37/32935 ,  H01J37/32972 ,  H01J37/3299

Abstract: A disclosed device comprises an edge bonding seal configured to be mounted to an edge bead of the electrostatic chuck. The edge bonding seal includes a monitoring layer comprised of a first material configured to either emit a species capable of being optically monitored or having an electrical resistance value capable of being monitored, or both. The edge bonding seal further includes an edge bonding layer configured to be interspersed at least between the monitoring layer and the plasma environment. The edge bonding layer is comprised of a second material susceptible to erosion due to reaction with the plasma environment and configured to expose the monitoring layer to the plasma environment upon sufficient exposure to the plasma environment.

Abstract translation: 所公开的装置包括构造成安装到静电卡盘的边缘珠缘上的边缘接合密封件。 边缘接合密封件包括由第一材料构成的监测层，该第一材料被配置为发射能够被光学监测的物质或具有能够被监测的电阻值，或两者。 边缘接合密封件还包括边缘粘合层，其被配置为至少散布在监测层和等离子体环境之间。 边缘粘合层由与等离子体环境的反应易受侵蚀的第二材料组成，并且被配置为在充分暴露于等离子体环境时将监测层暴露于等离子体环境。

公开(公告)号：US06716763B2

公开(公告)日：2004-04-06

申请号：US09991982

申请日：2001-11-26

Applicant: Li Li ,  Bradley J. Howard

Inventor： Li Li ,  Bradley J. Howard

IPC: H01L21302

CPC classification number: G03F7/40 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

公开(公告)号：US6028763A

公开(公告)日：2000-02-22

申请号：US61858

申请日：1998-04-17

Applicant: Bradley J. Howard

Inventor： Bradley J. Howard

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01G4/008 ,  H01G4/06

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82

Abstract: A capacitor and method for forming a capacitor is disclosed and which includes providing a node to which electrical connection is to be made; forming a first layer of conductive material to a first thickness over and in electrical connection with the node; forming a second layer of insulative material to a second thickness over the first layer, the second thickness being greater than the first thickness; forming a third layer of conductive material to a third thickness over the second layer; forming the first, second and third layers into a first capacitor plate; and forming a capacitor dielectric layer and second capacitor plate operatively adjacent the first capacitor plate.

Abstract translation: 公开了一种用于形成电容器的电容器和方法，其包括提供将要进行电连接的节点; 在所述节点上形成与所述节点电连接的第一厚度的第一层导电材料; 在所述第一层上形成第二厚度的第二绝缘材料层，所述第二厚度大于所述第一厚度; 在第二层上形成第三层导电材料至第三厚度; 将第一，第二和第三层形成第一电容器板; 以及形成与第一电容器板可操作地相邻的电容器电介质层和第二电容器板。

公开(公告)号：US5750441A

公开(公告)日：1998-05-12

申请号：US650723

申请日：1996-05-20

Applicant: Thomas A. Figura ,  Bradley J. Howard

Inventor： Thomas A. Figura ,  Bradley J. Howard

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76804

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract translation: 用于提高与下层的接触精度的方法和装置包括以下步骤：在下层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成掩模层，然后在掩模层上形成图案化的第二光致抗蚀剂层 。 使用第二光致抗蚀剂层作为图案对掩模层进行图案化，然后使用掩模层作为图案来对第一光致抗蚀剂层进行图案化。 在第一光致抗蚀剂层中形成锥形孔，例如使用各向异性蚀刻。 锥形孔具有靠近下层的底部，并且顶部远离下面的层，孔的顶部比孔的底部更宽。

公开(公告)号：US5711851A

公开(公告)日：1998-01-27

申请号：US679295

申请日：1996-07-12

Applicant: Guy T. Blalock ,  Bradley J. Howard

Inventor： Guy T. Blalock ,  Bradley J. Howard

IPC: H01L21/311 ,  H01L21/00

CPC classification number: H01L21/31116

Abstract: The temperature of a dry etch process of a semiconductor substrate in a plasma etch chamber is controlled to maintain selectivity while also providing a high etch rate by introducing one or more cooling steps into the etch process. To maintain selectivity of the etch as well as a high rate of etch, the formation of plasma is terminated prior to exceeding a predetermined maximum temperature at at least one selected location in the chamber. The temperature at the selected location is reduced prior to the resumption of plasma flow and etching. The plasma etch is then continued, and may optionally be terminated again to permit cooling, as needed, until etching has been completed.

Abstract translation: 控制等离子体蚀刻室中的半导体衬底的干蚀刻工艺的温度以保持选择性，同时通过将一个或多个冷却步骤引入到蚀刻工艺中来提供高蚀刻速率。 为了保持蚀刻的选择性以及高的蚀刻速率，等离子体的形成在超过腔室中的至少一个选定位置处的预定最大温度之前终止。 在等离子体流动和蚀刻恢复之前，所选位置处的温度降低。 然后继续等离子体蚀刻，并且可以根据需要可选地再次终止以允许冷却，直到蚀刻完成。

公开(公告)号：US08093155B2

公开(公告)日：2012-01-10

申请号：US12326834

申请日：2008-12-02

Applicant: Li Li ,  Bradley J. Howard

Inventor： Li Li ,  Bradley J. Howard

IPC: H01L21/02 ,  H01L21/311

CPC classification number: G03F7/40 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract translation: 公开了一种用于控制等离子体蚀刻方法中的条纹和CD损耗的方法。 在蚀刻工艺期间，待蚀刻的半导体材料的衬底首先在低功率冲击下暴露于等离子体，然后暴露于传统的高功率冲击。 已经发现CD损耗减少约400埃，并且在接触孔中形成的条纹减小。

公开(公告)号：US07573116B2

公开(公告)日：2009-08-11

申请号：US11506297

申请日：2006-08-18

Applicant: Bradley J. Howard ,  Dinesh Chopra

Inventor： Bradley J. Howard ,  Dinesh Chopra

IPC: H01L21/461

CPC classification number: H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76888

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer may be formed to electrically short the upper and lower portions of the sidewall and eliminate the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and structures are described.

Abstract translation: 用于制造半导体器件的方法包括蚀刻电介质层，导致在蚀刻期间沿着形成在电介质层中的侧壁的不期望的电荷积聚。 沿着侧壁的顶部和底部的电荷累积可以降低蚀刻速率，从而导致过多的蚀刻时间和不期望的蚀刻开口轮廓。 为了去除电荷，可以形成牺牲导电层以使侧壁的上部和下部电气短路并消除电荷。 在另一个实施例中，使用气体去除电荷。 在去除电荷之后，电介质蚀刻可以继续。 描述本发明方法和结构的各种实施方案。