公开(公告)号：US20060079053A1

公开(公告)日：2006-04-13

申请号：US10962008

申请日：2004-10-08

Applicant: Bomy Chen ,  Dana Lee ,  Yaw Hu ,  Bing Yeh

Inventor： Bomy Chen ,  Dana Lee ,  Yaw Hu ,  Bing Yeh

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L21/28114 ,  H01L27/11568 ,  H01L29/66553

Abstract: A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.

Abstract translation: 一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和 导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸， 电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

公开(公告)号：US06806531B1

公开(公告)日：2004-10-19

申请号：US10409248

申请日：2003-04-07

Applicant: Bomy Chen ,  Dana Lee ,  Bing Yeh

Inventor： Bomy Chen ,  Dana Lee ,  Bing Yeh

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.

公开(公告)号：US20070210369A1

公开(公告)日：2007-09-13

申请号：US11375386

申请日：2006-03-13

Applicant: Bomy Chen ,  Yaw Hu ,  Dana Lee

Inventor： Bomy Chen ,  Yaw Hu ,  Dana Lee

IPC: H01L29/788

CPC classification number: H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324

Abstract: A non-volatile floating gate memory cell, having a single polysilicon gate, compatible with conventional logic processes, comprises a substrate of a first conductivity type. A first and a second region of a second conductivity type are in the substrate, spaced apart from one another to define a channel region therebetween. A first gate is insulated from the substrate and is positioned over a first portion of the channel region and over the first region and is substantially capacitively coupled thereto. A second gate is insulated from the substrate, and is spaced apart from the first gate and is positioned over a second portion of the channel region, different from the first portion, and has little or no overlap with the second region.

Abstract translation: 具有与常规逻辑处理兼容的单个多晶硅栅极的非易失性浮动栅极存储单元包括第一导电类型的衬底。 第二导电类型的第一和第二区域在衬底中，彼此间隔开以限定它们之间的沟道区域。 第一栅极与衬底绝缘并且被定位在沟道区域的第一部分上方并且超过第一区域并且基本上电容耦合到其上。 第二栅极与衬底绝缘，并且与第一栅极间隔开并且位于与第一部分不同的沟道区域的第二部分上方，并且与第二区域几乎没有或没有重叠。

公开(公告)号：US06913975B2

公开(公告)日：2005-07-05

申请号：US10885923

申请日：2004-07-06

Applicant: Bomy Chen ,  Dana Lee ,  Bing Yeh

Inventor： Bomy Chen ,  Dana Lee ,  Bing Yeh

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.

Abstract translation: 非易失性存储单元具有第一导电类型的单结晶硅单晶硅。 在半导体材料中形成有彼此间隔开的与第一导电类型不同的第二导电类型的第一和第二区域。 具有第一部分的通道区域和第二部分连接用于电荷传导的第一和第二区域。 电介质在沟道区上。 可以是导电或非导电的浮动栅极位于电介质上，与沟道区的第一部分间隔开。 沟道区域的第一部分与第一区域相邻，第一浮栅具有大致三角形形状。 浮动门形成在空腔中。 栅极电极电容耦合到第一浮动栅极，并且与沟道区域的第二部分间隔开。 沟道区域的第二部分在第一部分和第二区域之间。 双向非易失性存储单元具有分别形成在空腔中的两个浮动栅极。 还公开了制造非易失性存储单元和阵列的方法。

公开(公告)号：US07119396B2

公开(公告)日：2006-10-10

申请号：US10962008

申请日：2004-10-08

Applicant: Bomy Chen ,  Dana Lee ,  Yaw Wen Hu ,  Bing Yeh

Inventor： Bomy Chen ,  Dana Lee ,  Yaw Wen Hu ,  Bing Yeh

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L21/28114 ,  H01L27/11568 ,  H01L29/66553

Abstract: A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.

Abstract translation: 一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和 导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸， 电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

公开(公告)号：US20070007581A1

公开(公告)日：2007-01-11

申请号：US11520993

申请日：2006-09-14

Applicant: Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

Inventor： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

Abstract: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

Abstract translation: 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

公开(公告)号：US20060043459A1

公开(公告)日：2006-03-02

申请号：US10934246

申请日：2004-09-02

Applicant: Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

Inventor： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

Abstract: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

公开(公告)号：US07180127B2

公开(公告)日：2007-02-20

申请号：US10872052

申请日：2004-06-17

Applicant: Bomy Chen ,  Dana Lee

Inventor： Bomy Chen ,  Dana Lee

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7885

Abstract: A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.

Abstract translation: 一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。 浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。 横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。 控制门围绕横向突起形成并与其绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。

公开(公告)号：US06992909B2

公开(公告)日：2006-01-31

申请号：US11157318

申请日：2005-06-20

Applicant: Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

Inventor： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

IPC: G11C17/00

CPC classification number: H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

Abstract translation: 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US20050104116A1

公开(公告)日：2005-05-19

申请号：US10714243

申请日：2003-11-13

Applicant: Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

Inventor： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

Abstract: A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

Abstract translation: 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。