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    CMOS transistor and method for fabricating the same
    2.
    发明授权
    CMOS transistor and method for fabricating the same 有权
    CMOS晶体管及其制造方法

    公开(公告)号：US09006059B2

    公开(公告)日：2015-04-14

    申请号：US14019724

    申请日：2013-09-06

    Applicant: Boe Technology Group Co., Ltd.

    Inventor： Bing Sun

    IPC: H01L21/8238 ,  H01L29/786 ,  H01L27/12

    CPC classification number: H01L21/823807 ,  H01L27/1288 ,  H01L29/78621

    Abstract: The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel.

    Abstract translation: 本发明提供一种CMOS晶体管的制造方法及阵列基板的制造方法。 制造CMOS晶体管的方法包括形成通道的步骤，包括：在衬底上沉积非晶硅层，并将非晶硅层结晶成多晶硅层; 将硼原子注入到多晶硅层中，然后通过蚀刻注入硼原子的多晶硅层形成N沟道区和P沟道区; 通过单一图案化工艺形成对应于N沟道区的光致抗蚀剂部分保留区域和对应于P沟道区的光致抗蚀剂完全保留区域; 并且去除光致抗蚀剂部分保留区域中的光致抗蚀剂并且使用灰化处理将光致抗蚀剂完全保留区域中的一部分光致抗蚀剂保持在光致抗蚀剂完全保留区域中，通过离子注入植入磷原子，从而形成N沟道和P沟道。

    Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
    3.
    发明授权
    Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device 有权
    薄膜晶体管及其制造方法，阵列基板及其制造方法以及显示装置

    公开(公告)号：US09455324B2

    公开(公告)日：2016-09-27

    申请号：US14376028

    申请日：2013-11-27

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Zhanfeng Cao ,  Qi Yao ,  Luke Ding ,  Bing Sun ,  Xiangchun Kong

    IPC: H01L29/423 ,  H01L27/12 ,  H01L29/51 ,  G02F1/1368 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/42364 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2029/42388

    Abstract: The present invention provides a thin film transistor and a method of fabricating the thin film transistor, an array substrate and a method of fabricating the array substrate, and a display device. The thin film transistor includes a substrate and a gate, an insulation layer, an active layer, a source and a drain which are provided on the substrate. A spacer layer is also provided between the gate and the active layer, and the spacer layer overlaps at least with one of the gate and the active layer having a smaller area in an orthographic projection direction. The spacer layer can effectively prevent material forming the gate from being diffused into the active layer, thereby ensuring stability of performance of the thin film transistor. In the array substrate utilizing the thin film transistor, the spacer layer further extends to a region corresponding to a gate line.

    Abstract translation: 本发明提供一种薄膜晶体管和制造薄膜晶体管的方法，阵列基板和制造阵列基板的方法以及显示装置。 薄膜晶体管包括设置在基板上的基板和栅极，绝缘层，有源层，源极和漏极。 间隔层还设置在栅极和有源层之间，并且间隔层至少与栅极和有源层中的一个重叠，在正投影方向上具有较小的面积。 间隔层可以有效地防止形成栅极的材料扩散到有源层中，从而确保薄膜晶体管的性能的稳定性。 在利用薄膜晶体管的阵列基板中，间隔层进一步延伸到对应于栅极线的区域。

    SHEET RESISTANCE MEASURING METHOD
    4.
    发明申请
    SHEET RESISTANCE MEASURING METHOD 有权
    表面电阻测量方法

    公开(公告)号：US20150260670A1

    公开(公告)日：2015-09-17

    申请号：US14470902

    申请日：2014-08-27

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Shi Shu ,  Bing Sun ,  Bin Zhang ,  Kexin Lu ,  Yue Shi ,  Zhijun LV

    IPC: G01N27/04

    CPC classification number: G01N27/041 ,  G01R27/00 ,  G01R27/04

    Abstract: The present disclosure relates to a sheet resistance measuring method, comprising the following steps: connecting at least one to-be-measured thin film having a predetermined shape to two separate electrodes in at least one pair of electrodes; measuring the resistance between the two electrodes in each pair of electrodes; and determining the sheet resistance of the to-be-measured thin film based on the measured resistance and the shape of the corresponding to-be-measured thin film.

    Abstract translation: 本发明涉及一种薄层电阻测量方法，包括以下步骤：在至少一对电极中将至少一个具有预定形状的被测量薄膜连接到两个分开的电极; 测量每对电极中的两个电极之间的电阻; 以及基于所测量的电阻和相应的待测薄膜的形状来确定待测薄膜的薄层电阻。

    Array substrate, manufacturing method therefor and display device
    5.
    发明授权
    Array substrate, manufacturing method therefor and display device 有权

    公开(公告)号：US09786506B2

    公开(公告)日：2017-10-10

    申请号：US14125648

    申请日：2012-11-15

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Bing Sun

    IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L27/12

    CPC classification number: H01L21/28008 ,  H01L27/124 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/4908

    Abstract: Provided is a manufacturing method for an array substrate, which relates to the technical field of displaying and comprises the steps of: S1: forming a pattern which comprises a first gate electrode (2) on a substrate (1); S2: forming a second gate electrode (4) above the first gate electrode (2) on the substrate (1) after step S1, and conducting oxidation treatment on the surface of the second gate electrode (4) to form a gate-insulating layer, the first gate electrode (2) and the second gate electrode (4) forming a gate electrode together; and S3: forming a layer-level structure of a pattern which comprises an active layer, source and drain electrodes, a data line, a passivation layer and a pixel electrode on the substrate after step S2. Also provided are an array substrate and a display device.

    ARRAY SUBSTRATE, MANUFACTURING METHOD THEREFOR AND DISPLAY DEVICE
    7.
    发明申请
    ARRAY SUBSTRATE, MANUFACTURING METHOD THEREFOR AND DISPLAY DEVICE 有权
    阵列基板，其制造方法及其显示装置

    公开(公告)号：US20140110719A1

    公开(公告)日：2014-04-24

    申请号：US14125648

    申请日：2012-11-15

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Bing Sun

    IPC: H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/28008 ,  H01L27/124 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/4908

    Abstract: Provided is a manufacturing method for an array substrate, which relates to the technical field of displaying and comprises the steps of: S1: forming a pattern which comprises a first gate electrode (2) on a substrate (1); S2: forming a second gate electrode (4) above the first gate electrode (2) on the substrate (1) after step S1, and conducting oxidation treatment on the surface of the second gate electrode (4) to form a gate-insulating layer, the first gate electrode (2) and the second gate electrode (4) forming a gate electrode together; and S3: forming a layer-level structure of a pattern which comprises an active layer, source and drain electrodes, a data line, a passivation layer and a pixel electrode on the substrate after step S2. Also provided are an array substrate and a display device.

    Abstract translation: 提供一种阵列基板的制造方法，其涉及显示技术领域，包括以下步骤：S1：在基板（1）上形成包括第一栅电极（2）的图案; S2：在步骤S1之后在基板（1）上形成位于第一栅电极（2）上方的第二栅电极（4），并在第二栅电极（4）的表面上进行氧化处理，以形成栅极绝缘层 ，第一栅电极（2）和第二栅电极（4）一起形成栅电极; 和S3：在步骤S2之后，在衬底上形成包括有源层，源极和漏极，数据线，钝化层和像素电极的图案层级结构。 还提供了阵列基板和显示装置。

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