Double and triple gate MOSFET devices and methods for making same
    1.
    发明授权
    Double and triple gate MOSFET devices and methods for making same 有权
    双栅极和三栅极MOSFET器件及其制造方法

    公开(公告)号:US08222680B2

    公开(公告)日:2012-07-17

    申请号:US10274961

    申请日:2002-10-22

    IPC分类号: H01L29/72

    摘要: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

    摘要翻译: 双栅极金属氧化物半导体场效应晶体管(MOSFET)包括鳍状物,第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中,三栅极MOSFET包括鳍片,第一栅极,第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

    Double and triple gate MOSFET devices and methods for making same
    4.
    发明授权
    Double and triple gate MOSFET devices and methods for making same 有权
    双栅极和三栅极MOSFET器件及其制造方法

    公开(公告)号:US08580660B2

    公开(公告)日:2013-11-12

    申请号:US13523603

    申请日:2012-06-14

    IPC分类号: H01L29/72

    摘要: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

    摘要翻译: 双栅极金属氧化物半导体场效应晶体管(MOSFET)包括鳍状物,第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中,三栅极MOSFET包括鳍片,第一栅极,第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

    Etch stop layer for etching FinFET gate over a large topography
    6.
    发明授权
    Etch stop layer for etching FinFET gate over a large topography 有权
    蚀刻停止层,用于在大地形上蚀刻FinFET栅极

    公开(公告)号:US06787476B1

    公开(公告)日:2004-09-07

    申请号:US10632989

    申请日:2003-08-04

    IPC分类号: H01L21302

    摘要: A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.

    摘要翻译: 提供了一种形成Fin场效应晶体管(FinFET)的栅极的方法。 该方法包括在翅片上形成第一层材料,并在第一层上形成第二层。 第二层包括Ti或TiN。 该方法还包括在第二层上形成第三层。 第三层包括抗反射涂层。 该方法还包括蚀刻第一,第二和第三层以形成用于FinFET的栅极。

    Scanning laser thermal annealing
    7.
    发明授权
    Scanning laser thermal annealing 有权
    扫描激光热退火

    公开(公告)号:US07351638B1

    公开(公告)日:2008-04-01

    申请号:US10021782

    申请日:2001-12-18

    IPC分类号: H01L21/336

    摘要: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

    摘要翻译: 一种制造半导体器件的方法包括在衬底上形成栅电极,将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。 在退火期间,激光器和衬底相对于彼此移动,并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断, 漏区。 来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分,并且激光器的斑点面积小于50毫米2。

    Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
    8.
    发明授权
    Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices 有权
    平面化牺牲氧化物以改善半导体器件中的栅极临界尺寸

    公开(公告)号:US07091068B1

    公开(公告)日:2006-08-15

    申请号:US10310776

    申请日:2002-12-06

    IPC分类号: H01L21/00

    CPC分类号: H01L29/785 H01L29/66795

    摘要: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.

    摘要翻译: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构,并在栅极结构上沉积栅极材料。 该方法还可以包括在栅极材料上形成牺牲材料并平坦化牺牲材料。 可以在平坦化的牺牲材料上沉积抗反射涂层。 然后可以通过蚀刻栅极材料形成栅极结构。