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1.发明授权Method and circuit for local clock generation and smartcard including it thereon 有权用于本地时钟产生的方法和电路以及包括其上的智能卡公开(公告)号：US07881894B2
公开(公告)日：2011-02-01
申请号：US12089897
申请日：2006-06-10
申请人： Robert Leydier , Alain Pomet , Benjamin Duval
发明人： Robert Leydier , Alain Pomet , Benjamin Duval
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/133 , H03K5/135 , H03K5/156 , H03K2005/00058 , H04L7/0338
摘要： One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i−1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i−1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i−1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
摘要翻译： 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号（0）到＆phgr;（2i-1）被提供有基本的时间步。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 将振荡器信号＆phgr（0）〜j（2i-1）变换成具有与所述时钟信号的有效边沿同步的时钟信号CK与至少一个振荡器信号（0）到（2i-1） 两个连续的有效边沿被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。
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公开(公告)号：US20100281197A1
公开(公告)日：2010-11-04
申请号：US12809898
申请日：2007-12-21
申请人： Robert Leydier , Alain Pomet , Benjamin Duval
发明人： Robert Leydier , Alain Pomet , Benjamin Duval
CPC分类号： G06F13/4027
摘要： A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.
摘要翻译： 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。
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3.发明申请Method and Circuit for Local Clock Generation and Smartcard Including it Thereon 有权本地时钟产生方法和电路及其中包含的智能卡公开(公告)号：US20080231328A1
公开(公告)日：2008-09-25
申请号：US12089897
申请日：2006-06-10
申请人： Robert Leydier , Alain Pomet , Benjamin Duval
发明人： Robert Leydier , Alain Pomet , Benjamin Duval
IPC分类号： H03B21/00 , G06F1/04 , G06K19/067
CPC分类号： G06F1/04 , H03K5/133 , H03K5/135 , H03K5/156 , H03K2005/00058 , H04L7/0338
摘要： One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
摘要翻译： 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号phi（0）到phi（2I i-1）被提供有基本的时间步骤。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 振荡器信号phi（0）至j（2-i-1）被转换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号phi（0）至phi （2 1>），两个连续的有效边沿被分开与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。
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公开(公告)号：US07836239B2
公开(公告)日：2010-11-16
申请号：US11462110
申请日：2006-08-03
申请人： Benjamin Duval , Alain Pomet
发明人： Benjamin Duval , Alain Pomet
CPC分类号： G06F13/4081
摘要： A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.
摘要翻译： 一个设备包括一个串行端口，用于通过串行链路作为从设备连接到主设备。 该装置还包括检测电路，用于检测与串行端口的端子相连接的主设备的阻抗的存在。 该设备可以与包含USB端口的微处理器卡一起使用。
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5.发明授权Electronic circuit with means of evaluating its temperature, method for evaluating the temperature, and application 有权具有评估其温度的电子电路，用于评估温度的方法和应用公开(公告)号：US07283007B2
公开(公告)日：2007-10-16
申请号：US11202392
申请日：2005-08-11
申请人： Benjamin Duval , Alain Pomet
发明人： Benjamin Duval , Alain Pomet
IPC分类号： H03L1/00
摘要： An electronic circuit (CE) is provided with an oscillator (OSC—1) outputting a signal (S1) with a frequency (F1) varying as a function of the temperature (Tc) of this circuit, and receiving or outputting a signal (S2) with a fixed and known frequency (F2). This circuit includes a measurement module (MSR) outputting a measurement signal (Φ1) representative of the variable frequency (F1) evaluated using the fixed frequency signal (S2) used as a reference or standard, and a conversion module (CVRS) applying a transfer function (u−1, v−1, or w−1) that is the inverse of the function for the variation of the frequency of the first signal (S1) as a function of the temperature, to the measurement signal (Φ1), in order to output a signal (Φc) representative of the circuit temperature (Tc).
摘要翻译： 电子电路（CE）设置有输出频率（F 1）的信号（S 1）的振荡器（OSC-1），该频率（F1）作为该电路的温度（Tc）的函数而变化 ，并且接收或输出具有固定和已知频率（F 2）的信号（S 2）。 该电路包括输出表示使用用作基准或标准的固定频率信号（S 2）评估的可变频率（F 1）的测量信号（Phi 1）的测量模块（MSR）和转换模块（CVRS） 施加作为变化函数的函数的倒数的传递函数（u -1 ，V SUP = -1或<！ - SIPO
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6.发明申请Electronic circuit with means of evaluating its temperature, method for evaluating the temperature, and application 有权具有评估其温度的电子电路，用于评估温度的方法和应用公开(公告)号：US20060038626A1
公开(公告)日：2006-02-23
申请号：US11202392
申请日：2005-08-11
申请人： Benjamin Duval , Alain Pomet
发明人： Benjamin Duval , Alain Pomet
IPC分类号： H03L1/00
摘要： An electronic circuit (CE) is provided with an oscillator (OSC—1) outputting a signal (S1) with a frequency (F1) varying as a function of the temperature (Tc) of this circuit, and receiving or outputting a signal (S2) with a fixed and known frequency (F2). This circuit includes a measurement module (MSR) outputting a measurement signal (Φ1) representative of the variable frequency (F1) evaluated using the fixed frequency signal (S2) used as a reference or standard, and a conversion module (CVRS) applying a transfer function (u−1, v−1, or w−1) that is the inverse of the function for the variation of the frequency of the first signal (S1) as a function of the temperature, to the measurement signal (Φ1), in order to output a signal (Φc) representative of the circuit temperature (Tc).
摘要翻译： 电子电路（CE）设置有输出频率（F 1）的信号（S 1）的振荡器（OSC-1），该频率（F1）作为该电路的温度（Tc）的函数而变化 ，并且接收或输出具有固定和已知频率（F 2）的信号（S 2）。 该电路包括输出表示使用用作基准或标准的固定频率信号（S 2）评估的可变频率（F 1）的测量信号（Phi 1）的测量模块（MSR）和转换模块（CVRS） 施加作为变化函数的函数的倒数的传递函数（u -1 ，V SUP = -1或<！ - SIPO
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公开(公告)号：US08412873B2
公开(公告)日：2013-04-02
申请号：US12809898
申请日：2007-12-21
申请人： Robert Leydier , Alain Pomet , Benjamin Duval
发明人： Robert Leydier , Alain Pomet , Benjamin Duval
CPC分类号： G06F13/4027
摘要： A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.
摘要翻译： 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。
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8.发明授权Method and device for generating a random number in a USB (universal serial bus) peripheral 有权用于在USB（通用串行总线）外设中产生随机数的方法和装置公开(公告)号：US07958175B2
公开(公告)日：2011-06-07
申请号：US11653185
申请日：2007-01-12
申请人： Alain Pomet , Benjamin Duval , Robert Leydier
发明人： Alain Pomet , Benjamin Duval , Robert Leydier
IPC分类号： G06F1/02
CPC分类号： G06F7/588
摘要： A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.
摘要翻译： 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。
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9.发明申请Method and device for generating a random number in a USB (Universal Serial Bus) peripheral 有权用于在USB（通用串行总线）外设中产生随机数的方法和装置公开(公告)号：US20090089347A1
公开(公告)日：2009-04-02
申请号：US11653185
申请日：2007-01-12
申请人： Alain Pomet , Benjamin Duval , Robert Leydier
发明人： Alain Pomet , Benjamin Duval , Robert Leydier
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.
摘要翻译： 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。
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公开(公告)号：US20070106825A1
公开(公告)日：2007-05-10
申请号：US11462110
申请日：2006-08-03
申请人： Benjamin Duval , Alain Pomet
发明人： Benjamin Duval , Alain Pomet
IPC分类号： G06F13/42
CPC分类号： G06F13/4081
摘要： A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.
摘要翻译： 一个设备包括一个串行端口，用于通过串行链路作为从设备连接到主设备。 该装置还包括检测电路，用于检测与串行端口的端子相连接的主设备的阻抗的存在。 该设备可以与包含USB端口的微处理器卡一起使用。
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