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公开(公告)号：US11360915B2
公开(公告)日：2022-06-14
申请号：US16904856
申请日：2020-06-18
Inventor： Xianglun Leng , Ningyi Xu , Yang Yan , Zhengze Qiu , Wei Qi
IPC: G06F3/06 , G06F13/16 , H04L41/0896
Abstract: According to embodiments of the present disclosure, there is provided a data transmission apparatus. The data transmission apparatus includes a plurality of first ports, a plurality of second ports, and a plurality of data channels. The plurality of first ports are coupled to a processing unit. The plurality of second ports are coupled to a plurality of memories. The plurality of data channels are disposed among the first ports and the second ports to form an interleaving network having a plurality of layers, and configured to transmit data among the processing unit and the plurality of memories, such that each layer in the interleaving network includes at least one interleaving sub-network.
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Patent Agency Ranking
2.发明授权公开(公告)号：US11372673B2
公开(公告)日：2022-06-28
申请号：US16505127
申请日：2019-07-08
Inventor： Ningyi Xu , Yan Huang , Jinchen Han , Peng Wu , Jiaxin Shi
Abstract: Embodiments of the present disclosure disclose an artificial intelligence chip and an instruction execution method for an artificial intelligence chip. A specific embodiment of the artificial intelligence chip includes: an instruction memory, a data memory, at least one general execution unit, and at least one dedicated execution unit. The instruction memory is configured to: receive a kernel code including at least one code block. The general execution unit is configured to: receive the code block, lock the dedicated execution unit associated with the received code block, and send an instruction in the received code block to the locked dedicated execution unit. The dedicated execution unit is configured to: execute the received instruction, and store an execution result in the data memory. The data memory is configured to: store the execution result sent by the dedicated execution unit.
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公开(公告)号：US11023391B2
公开(公告)日：2021-06-01
申请号：US16506151
申请日：2019-07-09
Inventor： Peng Wu , Jian Ouyang , Canghai Gu , Wei Qi , Ningyi Xu
Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
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公开(公告)号：US20200050557A1
公开(公告)日：2020-02-13
申请号：US16506151
申请日：2019-07-09
Inventor： Peng Wu , Jian Ouyang , Canghai Gu , Wei Qi , Ningyi Xu
Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
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5.发明授权公开(公告)号：US11485376B2
公开(公告)日：2022-11-01
申请号：US16711187
申请日：2019-12-11
Inventor： Chongqin Wang , Zhibiao Zhao , Hefei Zhu , Ningyi Xu , Jian Ouyang
IPC: B60W50/04 , B60W50/02 , B60W50/035
Abstract: An automatic processing system, a system on chip and a method for monitoring a processing module are described herein. The automatic driving processing system comprises: an automatic driving processing module, configured for receiving an input data stream and processing the input data stream based on a deep learning model so as to generate a processing result; a fault detection module, configured for generating a control signal and a fault detection stimulating data stream, and receiving the processing result from the automatic driving processing module; and a multi-way selection module, configured for receiving an automatic driving data stream as well as the control signal and the fault detection stimulating data stream, and selectively outputting the automatic driving data stream or the fault detection stimulating data stream to the automatic driving processing module based on the control signal, as an input data stream.
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6.发明申请公开(公告)号：US20200050476A1
公开(公告)日：2020-02-13
申请号：US16505127
申请日：2019-07-08
Inventor： Ningyi Xu , Yan Huang , Jinchen Han , Peng Wu , Jiaxin Shi
Abstract: Embodiments of the present disclosure disclose an artificial intelligence chip and an instruction execution method for an artificial intelligence chip. A specific embodiment of the artificial intelligence chip includes: an instruction memory, a data memory, at least one general execution unit, and at least one dedicated execution unit. The instruction memory is configured to: receive a kernel code including at least one code block. The general execution unit is configured to: receive the code block, lock the dedicated execution unit associated with the received code block, and send an instruction in the received code block to the locked dedicated execution unit. The dedicated execution unit is configured to: execute the received instruction, and store an execution result in the data memory. The data memory is configured to: store the execution result sent by the dedicated execution unit.
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